CN110136630A - A kind of display panel and its driving method, display device - Google Patents

Abstract

A display panel, a driving method thereof, and a display device, wherein the display panel comprises: M rows and N columns of pixel units, M+1 rows of scan lines, N columns of data lines, a multiplexing circuit and a source drive circuit, the i-th row The pixel unit is connected to the scan line of the i-th row and the scan line of the i+1-th row respectively; the pixel unit of the j-th column is connected to the data line of the j-th column, 1≤i≤M, 1≤j≤N, the multiplexing circuit, It is respectively connected with the selection control terminal, the source driving circuit and the N column data lines, and is used for inputting the data signal output by the source driving circuit into the corresponding data line in time division under the control of the selection control terminal. In the technical solution provided by the present application, each row of pixel units is connected to two rows of scan lines, and the use of multiplexers can reduce the difference in charging rates of pixel units in different columns, avoid vertical stripes, and improve the display panel. display effect.

Description

A display panel, a driving method thereof, and a display device

technical field

This document relates to the field of display technology, and in particular, to a display panel, a method for driving the same, and a display device.

Background technique

With the continuous development of display technology, the display panels used to display images are also varied, and can display colorful images. Specifically, the display panel includes: a pixel unit, horizontal and vertical scanning lines and data lines, a gate driving circuit and a source driving circuit. The source driving circuit is used for providing data signals to the data lines, and the gate driving circuit is used for one by one. The scanning lines are scanned in rows to provide data signals to the pixel units and finally realize the normal display of images, wherein the source driver circuit includes: a plurality of source driver chips.

In order to realize the narrow frame of the display panel, the display panels in the related art all use the multi-channel multiplexing technology, that is, each source driver chip in the display panel is connected to at least two columns of data lines. The charging rate of the pixel units in different columns of the display panel of the multiplexing technology is different, which in turn causes vertical stripes, which affects the display effect of the display panel.

SUMMARY OF THE INVENTION

The present application provides a display panel, a driving method thereof, and a display device, which can reduce the difference in the charging rates of pixel units in different columns, avoid vertical stripes, and further improve the display effect of the display panel.

In a first aspect, the present application provides a display panel, comprising: M rows and N columns of pixel units, M+1 rows of scan lines, N columns of data lines, a multiplexing circuit and a source driving circuit;

The i-th row of pixel units is connected to the i-th row scan line and the i+1-th row scan line respectively; the j-th column of pixel units is connected to the j-th column of data lines, 1≤i≤M, 1≤j≤N;

The multiplex selection circuit is respectively connected with the selection control terminal, the source driving circuit and the N column data lines, and is used for inputting the data signal output by the source driving circuit to the corresponding data line in time-division under the control of the selection control terminal middle.

Optionally, for the pixel unit of the ith row and the jth column, when j=4k+1 or 4k+2, the pixel unit of the ith row and the jth column is connected to the scan line of the ith row;

When j=4k+3 or 4k+4, the pixel unit of the i-th row and the j-th column is connected to the scan line of the i+1-th row, 0≤k<N/4.

Optionally, the s-th row scan line includes: a first sub-scan line and a second sub-scan line, 1<s≤M;

The first sub-scan line of the scan line in the s-th row is connected to the pixel unit in the s-1-th row and the t1-th column, where t1=4k+3 or 4k+4, 0≤k<N/4;

The second sub-scan line of the s-th row scan line is connected to the s-th row and the t2-th column pixel unit, wherein t2=4k+1 or 4k+2;

The scan line of the first row is connected to the pixel unit of the first row and the t2th column, and the scan line of the M+1th row is connected to the pixel unit of the Mth row and the t1th column.

Optionally, for the pixel unit of the i-th row and the j-th column, the pixel unit includes: a display element and a switch element, and the switch element includes: a first transistor;

When j=4k+1 or 4k+2, the control electrode of the first transistor is connected to the scan line of the i-th row, the first electrode of the first transistor is connected to the data line of the j-th column, and the second electrode of the first transistor is connected to the display line component connection;

When j=4k+3 or 4k+4, the control electrode of the first transistor is connected to the scan line of the i+1th row, the first electrode of the first transistor is connected to the data line of the jth column, and the second electrode of the first transistor is connected to the scan line of the i+1th row. Connect with the display element.

Optionally, the source drive circuit includes: P source drive units, the multiplexing circuit includes: Q selection circuits, the selection control terminal includes: Q selection control terminals, the selection control terminal and the selection control terminal One-to-one correspondence of circuits, where P×Q=N;

The i-th selection circuit is respectively connected to the corresponding selection control terminal, the P source driving units, the 2Qk+2i-1-th column data line and the 2Qk+2i-th column data line, where 1≤i≤Q, 0≤ k<N/2Q.

Optionally, the i-th selection circuit includes: P i+1-th transistors;

The control pole of the jth i+1th transistor is connected to the selection control terminal corresponding to the ith selection circuit, and the first pole of the jth i+1th transistor is connected to the jth source driving unit;

When j is an even number, the second pole of the jth i+1th transistor is connected to the data line of the (j-2)Q+2ith column; when j is an odd number, the second pole of the jth i+1th transistor is connected to the data line of the (j-2)Q+2ith column. The data lines of the (j-1)th Q+2i-1 column are connected, 1≤j≤P.

Optionally, the electrical signals on the adjacent plurality of data lines are arranged in sequence according to the arrangement order of positive polarity and negative polarity.

Optionally, the multiplexing circuit and the source driving circuit are located in a non-display area of the display panel.

In a second aspect, an embodiment of the present application further provides a display device, including: the above-mentioned display panel.

In a third aspect, an embodiment of the present application further provides a method for driving a display panel, which is used for driving the above-mentioned display panel, and the method includes:

Under the control of the selection control terminal, the multiplex selection circuit time-divisions and inputs the data signal output by the source driver circuit into the corresponding data line.

The present application provides a display panel, a driving method thereof, and a display device, wherein the display panel includes: M rows and N columns of pixel units, M+1 rows of scan lines, N columns of data lines, a multiplexing circuit, and a source driving circuit , the pixel unit of the i-th row is connected to the scan line of the i-th row and the scan line of the i+1-th row respectively; the pixel unit of the j-th column is connected to the data line of the j-th column, 1≤i≤M, 1≤j≤N, and more The channel selection circuit is respectively connected to the selection control terminal, the source driving circuit and the N column data lines, and is used for inputting the data signal output by the source driving circuit to the corresponding data line in time-division under the control of the selection control terminal. In the technical solution provided by the present application, each row of pixel units is connected to two rows of scan lines, and the use of multiplexers can reduce the difference in charging rates of pixel units in different columns, avoid vertical stripes, and improve the display panel. display effect.

Other features and advantages of the present application will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the present application. Other advantages of the present application may be realized and attained by the means described in the specification, claims and drawings.

Description of drawings

The accompanying drawings are used to provide an understanding of the technical solutions of the present application, and constitute a part of the specification. They are used to explain the technical solutions of the present application together with the embodiments of the present application, and do not constitute a limitation on the technical solutions of the present application.

1 is a schematic structural diagram of a display panel in the related art;

FIG. 2 is a working sequence diagram of the display panel provided in FIG. 1;

FIG. 3 is a schematic structural diagram 1 of a display panel provided by an embodiment of the present application;

FIG. 4 is a second schematic structural diagram of a display panel according to an embodiment of the present application

FIG. 5 is an equivalent circuit diagram 1 of a display panel provided by an embodiment of the present application;

FIG. 6 is an equivalent circuit diagram 2 of a display panel provided by an embodiment of the present application;

FIG. 7 is an equivalent circuit diagram 3 of the display panel provided by the embodiment of the present application;

FIG. 8 is a working sequence diagram of the display panel provided in FIG. 5;

FIG. 9 is an operation timing diagram of the display panel provided in FIG. 6 .

Detailed ways

This application describes a number of embodiments, but the description is exemplary rather than restrictive, and it will be apparent to those of ordinary skill in the art that within the scope of the embodiments described in this application can be There are many more examples and implementations. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are possible. Unless expressly limited, any feature or element of any embodiment may be used in combination with, or may be substituted for, any other feature or element of any other embodiment.

This application includes and contemplates combinations with features and elements known to those of ordinary skill in the art. The embodiments, features and elements that have been disclosed in this application can also be combined with any conventional features or elements to form unique inventive solutions as defined by the claims. Any features or elements of any embodiment may also be combined with features or elements from other inventive arrangements to form another unique inventive arrangement defined by the claims. Accordingly, it should be understood that any of the features shown and/or discussed in this application may be implemented alone or in any suitable combination. Accordingly, the embodiments are not to be limited except in accordance with the appended claims and their equivalents. Furthermore, various modifications and changes may be made within the scope of the appended claims.

Furthermore, in describing representative embodiments, the specification may have presented methods and/or processes as a particular sequence of steps. However, to the extent that the method or process does not depend on the specific order of steps described herein, the method or process should not be limited to the specific order of steps described. Other sequences of steps are possible, as will be understood by those of ordinary skill in the art. Therefore, the specific order of steps set forth in the specification should not be construed as limitations on the claims. Furthermore, the claims directed to the method and/or process should not be limited to performing their steps in the order written, as those skilled in the art will readily appreciate that these orders may be varied and still remain within the spirit and scope of the embodiments of the present application Inside.

Unless otherwise defined, technical or scientific terms used in the disclosure of the embodiments of the present invention shall have the ordinary meanings understood by those with ordinary skill in the art to which the present invention belongs. "First", "second" and similar words used in the embodiments of the present invention do not indicate any order, quantity or importance, but are only used to distinguish different components. "Comprising" or "comprising" and similar words mean that the elements or things appearing before the word encompass the elements or things recited after the word and their equivalents, but do not exclude other elements or things. Words like "connected" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

Those skilled in the art can understand that the transistors used in all the embodiments of the present application may be thin film transistors or field effect transistors or other devices with the same characteristics. Preferably, the thin film transistor used in the embodiments of the present invention may be an oxide semiconductor transistor. Since the source and drain of the transistor used here are symmetrical, the source and drain can be interchanged. In this embodiment of the present invention, in order to distinguish the two electrodes of the switching transistor except the gate, one electrode is called the first electrode, and the other electrode is called the second electrode. The diode can be a drain or a source.

FIG. 1 is a schematic structural diagram of a display panel in the related art. As shown in FIG. 1 , the display panel in the related art includes: a pixel unit 11 arranged in an array, a scan line Gate, a data line Data, and a first multiplexer 12 and the second multiplexer 13 and a plurality of source driving units S.

Among them, the first multiplexer 12 is connected to the first selection control terminal MUX1, and the second multiplexer 13 is connected to the second selection control terminal MUX2. It should be noted that each source driving unit in FIG. 1 is connected to the two The column data lines are connected. Taking the first source driving unit as an example, the first source driving unit S1 provides data signals to the red sub-pixel R through the first multiplexer 12, and sends the data signal to the red sub-pixel R through the second multiplexer 13. The blue sub-pixel B provides the data signal.

FIG. 2 is a working timing diagram of the display panel provided in FIG. 1. Combined with FIG. 1 and FIG. 2, the first four pixel units in the first row are displayed as an example, wherein the four pixel units include: two red sub-pixels, The red sub-pixel close to the green sub-pixel becomes the first red sub-pixel, and the other is called the second red sub-pixel. Specifically, the working process of the display panel in the related art includes:

In the first stage t1, the first selection control terminal MUX1 provides an active level, the first scan line Gate1 provides an active level, the first source driving unit S1 charges the first red sub-pixel, and the second source driving unit S2 Charge the green subpixel.

In the second stage t2, the first selection control terminal MUX1 provides an inactive level, the first source driving unit S1 stops charging the first red sub-pixel, and the second source driving unit S2 stops charging the green sub-pixel. A red sub-pixel and a green sub-pixel are affected by the storage capacitance of the first selection control terminal MUX1, and the pixel voltage is pulled and dropped by ΔV1. At this time, the second selection control terminal MUX2 provides an active level, and the first source is driven. The unit S1 charges the blue sub-pixel, and the second source driving unit S2 charges the second red sub-pixel.

After the second stage t2, the second selection control terminal MUX2 provides an inactive level, the first scan line Gate1 provides an inactive level, and the first red sub-pixel and green sub-pixel are affected by the storage capacitance of the first scan line Gate1, and the pixel The voltage is pulled for the second time and drops again by ΔV2, while the blue sub-pixel and the second red sub-pixel are only affected by the storage capacitance of the first scan line Gate1, and the pixel voltage is pulled once and drops by ΔV3. Since △V1+△V2≠△V3, the pixel voltages of the first red sub-pixel and the blue sub-pixel are different, so that the charging rates of the first red sub-pixel and the blue sub-pixel are different, and the macroscopic performance is The difference in brightness results in vertical stripes under the gray scale. In severe cases, flickering light and dark vertical stripes can be seen, which affects the display effect of the display panel.

In order to solve the above technical problems, the embodiments of the present application provide a display panel, a driving method thereof, and a display device, which are specifically described as follows:

Some embodiments of the present application provide a display panel. FIG. 3 is a schematic structural diagram 1 of the display panel provided by the embodiment of the present application. As shown in FIG. 3 , the display panel provided by the embodiment of the present application includes: M rows and N columns of pixel units 10 , M+1 rows of scan lines G1 to GM+1, N columns of data lines D1 to DN, multiplexing circuits and source drive circuits.

Specifically, the pixel unit in the ith row is connected to the scan line Gi in the i-th row and the scan line Gi+1 in the i+1-th row respectively; the pixel unit in the j-th column is connected with the data line Dj in the j-th column, 1≤i≤M, 1≤j≤N, the multiplex selection circuit is respectively connected with the selection control terminal MUX, the source driver circuit and the data lines D1~DN of the N columns, and is used for the output of the source driver circuit under the control of the selection control terminal MUX. The data signal is input to the corresponding data line in time division.

Specifically, the pixel units in the first row are respectively connected with the scan line G1 in the first row and the scan line G2 in the second row, and the pixel units in the second row are respectively connected with the scan line G2 in the second row and the scan line G3 in the third row. By analogy, the pixel units of the first column are connected to the data line D1 of the first column, the pixel units of the second column are connected to the data line D2 of the second column, and so on. It should be noted that both M and N are positive integers greater than or equal to 1, which are not limited in this application, and are specifically limited according to actual needs.

In the embodiment of the present application, the display panel includes: a display area and a non-display area, the scan lines, data lines and pixel units are located in the display area, and the multiplexing circuit and the source driving circuit are located in the non-display area of the display panel.

Specifically, the pixel unit in the embodiment of the present application is a sub-pixel, and the sub-pixel includes: a red sub-pixel R, a blue sub-pixel B, or a green sub-pixel G.

The display panel provided by the embodiments of the present application may adopt a low temperature polysilicon (Low Temperature Poly-silicon, LTPS for short) process or an oxide process.

Specifically, the multiplexing circuit includes: a plurality of signal input ends and a plurality of signal output ends, wherein the plurality of signal input ends are connected to the source driving circuit, and the number of the signal input ends is less than the number of the signal output ends. Disposing the multiplexing circuit in the display panel can reduce the size of the source driving circuit, thereby realizing a narrow frame of the display panel.

The display panel provided by the embodiment of the present application includes: M rows and N columns of pixel units, M+1 rows of scan lines, N columns of data lines, a multiplexing circuit and a source drive circuit, the i-th row of pixel units, which are respectively connected to the i-th row of pixel units. The scan line is connected to the scan line of the i+1th row; the pixel unit of the jth column is connected to the data line of the jth column, 1≤i≤M, 1≤j≤N, a multiplex selection circuit, which is respectively connected with the selection control terminal, the source electrode The driving circuit is connected to the data lines of the N columns, and is used for inputting the data signals output by the source driving circuit into the corresponding data lines in time division under the control of the selection control terminal. In the technical solution provided by the present application, each row of pixel units is connected to two rows of scan lines, and the use of multiplexers can reduce the difference in charging rates of pixel units in different columns, avoid vertical stripes, and improve the display panel. display effect.

Optionally, as shown in FIG. 3, for the pixel unit of the i-th row and the j-th column, when j=4k+1 or 4k+2, the i-th row and the j-th column of the pixel unit is connected to the i-th row scan line Gi, and when j=4k+1 or 4k+2 When j=4k+3 or 4k+4, the pixel unit in the i-th row and the j-th column is connected to the scan line Gi+1 in the i+1-th row, 0≤k<N/4.

Specifically, the pixel units in the first row and the first column are connected to the scan line G1 of the first row, the pixel units of the first row and the second column are connected to the scan line G2 of the first row, and the pixel units of the first row and the third column are connected to the scan line G2 of the second row. The line G2 is connected, the pixel units in the second row and the fourth column are connected with the scanning line G2 in the second row, and so on, which is not limited in the embodiment of the present application. It should be noted that each row of scan lines in FIG. 3 is a signal line.

Optionally, FIG. 4 is a second schematic structural diagram of a display panel provided by an embodiment of the present application. As shown in FIG. 4 , the scan line Gs in the s-th row includes: a first sub-scan line Gs1 and a second sub-scan line Gs2, 1< s≤M.

Specifically, the first sub-scan line Gs1 of the scan line Gs in the s-th row is connected to the pixel unit in the s-1-th row and the t1-th column. The sub-scan line Gs2 is connected to the pixel unit of the s-th row and the t2-th column, wherein t2=4k+1 or 4k+2, the scan line G1 of the first row is connected to the pixel unit of the first row and the t2-th column, and the M+1-th row scans The line is connected to the pixel unit of the Mth row and the t1th column.

Specifically, as shown in FIG. 4 , the scan line G2 in the second row includes: a first sub-scan line G21 and a second sub-scan line G22; The column pixel unit, the first row and the fourth column pixel unit, the first row and the seventh column pixel unit, the first row and the eighth column pixel unit, etc. are connected, and the second sub scan line G22 of the second row scan line G2 is connected to the second row The pixel units in the first column, the pixel units in the second row and the second column, the pixel units in the second row and the fifth column, and the pixel units in the second row and the sixth column are connected, and the scan line G3 in the third row includes: the first sub-scan line G31 and the The second sub-scan line G32, the first sub-scan line G31 of the third row of scan line G3 and the second row of the third column of pixel units, the second row of the fourth column of pixel units, the second row of the seventh column of pixel units, the second The pixel units in the eighth column of the row are connected, and the second sub-scan line G32 of the scan line G3 of the third row is connected to the pixel unit of the first column of the third row, the pixel unit of the second column of the third row, the pixel unit of the third row of the fifth column, The pixel units in the third row and the sixth column are connected and so on, and so on. It should be noted that the scan line in the first row and the scan line in the M+1th row in FIG. 4 are one signal line, and the scan lines except the scan line in the first row and the scan line in the M+1th row include two root signal line.

Optionally, as shown in FIGS. 3 and 4 , for the pixel unit of the i-th row and the j-th column, the pixel unit 10 includes: a display element 20 and a switch element.

Specifically, the switching element includes: a first transistor M1.

When j=4k+1 or 4k+2, the control electrode of the first transistor M1 is connected to the scan line Gi of the i-th row, the first electrode of the first transistor M1 is connected to the data line Dj of the j-th column, and the The second electrode is connected to the display element 20; when j=4k+3 or 4k+4, the control electrode of the first transistor M1 is connected to the scan line Gi+1 of the i+1th row, and the first electrode of the first transistor M1 is connected to The j-th column data line Dj is connected, and the second electrode of the first transistor M1 is connected to the display element 20 .

As shown in FIG. 3 and FIG. 4 , the technical solutions provided by the embodiments of the present application connect the switching elements in each row of pixel units so that the switching elements in each row of pixel units are arranged in a Z-shaped inverted structure.

Optionally, the electrical signals on the adjacent multiple data lines are arranged in sequence according to the arrangement order of positive polarity and negative polarity.

Optionally, FIG. 5 is an equivalent circuit diagram 1 of a display panel provided by an embodiment of the application, FIG. 6 is an equivalent circuit diagram 2 of a display panel provided by an embodiment of the application, and FIG. 7 is an equivalent circuit diagram of the display panel provided by the embodiment of the application. Equivalent circuit diagram 3, as shown in FIG. 5 , FIG. 6 and FIG. 7 , the source driver circuit provided by the embodiment of the present application includes: P source driver units S1 to SP, and the multiplexing circuit includes: Q selection circuits, The selection control terminal MUX includes: Q selection control terminals MUX1 to MUXQ, and the selection control terminals are in one-to-one correspondence with the selection circuit, wherein P×Q=N.

Specifically, the i-th selection circuit is respectively associated with the corresponding selection control terminal MUXi, the P source driving units S1-SP, the 2Qk+2i-1-th column data line, and the 2Qk+2i-th column data line, where 1≤ i≤Q, 0≤k<N/2Q.

Optionally, the i-th selection circuit includes: P i+1-th transistors Mi+1.

Specifically, the control pole of the jth i+1th transistor Mi+1 is connected to the selection control terminal MUXi corresponding to the ith selection circuit, and the first pole of the jth i+1th transistor Mi+1 is connected to the jth The source drive unit Sj is connected; when j is an even number, the second pole of the jth i+1th transistor Mi+1 is connected to the (j-2)Q+2ith column data line, when j is an odd number, the jth The second pole of the i+1th transistor is connected to the (j-1)Q+2i-1th column data line, 1≤j≤P.

It should be noted that, in FIG. 5 and FIG. 6 , Q=2 is used as an example for description, which is not limited in the embodiment of the present application. Specifically, the multiplexing circuit includes: a first selection circuit and a second selection circuit.

Wherein, the first selection circuit includes: P second transistors M2, the control electrode of the first second transistor M2 is connected to the first selection control terminal MUX1, and the first electrode thereof is connected to the first source driving unit S1, Its second pole is connected to the first column data line D1, the control pole of the second second transistor M2 is connected to the first selection control terminal MUX1, its first pole is connected to the second source driving unit S2, and its first pole is connected to the second source driving unit S2. The diode is connected to the second column data line D2, the control electrode of the third second transistor M2 is connected to the first selection control terminal MUX1, the first electrode is connected to the third source driving unit S3, and the second electrode is connected to the third source driving unit S3. It is connected to the data line D5 of the fifth column, and so on.

Wherein, the second selection circuit includes: P third transistors M3, the control electrode of the first third transistor M3 is connected to the second selection control terminal MUX2, and the first electrode thereof is connected to the first source driving unit S1, Its second pole is connected to the third column data line D3, the control pole of the second third transistor M3 is connected to the second selection control terminal MUX2, its first pole is connected to the second source driving unit S2, and its first pole is connected to the second source driving unit S2. The second electrode is connected to the fourth column data line D4, the control electrode of the third third transistor M3 is connected to the second selection control terminal MUX2, the first electrode is connected to the third source driving unit S3, and the second electrode is connected to the third source driving unit S3. It is connected to the data line D7 of the seventh column, and so on.

It should be noted that FIG. 7 takes Q=3 as an example for description, which is not limited in any embodiment of the present application. Specifically, the multiplexing circuit includes: a first selection circuit, a second selection circuit and a third selection circuit.

Wherein, the first selection circuit includes: P second transistors M2, the control electrode of the first second transistor M2 is connected to the first selection control terminal MUX1, and the first electrode thereof is connected to the first source driving unit S1, Its second pole is connected to the first column data line D1, the control pole of the second second transistor M2 is connected to the first selection control terminal MUX1, its first pole is connected to the second source driving unit S2, and its first pole is connected to the second source driving unit S2. The diode is connected to the second column data line D2, the control electrode of the third second transistor M2 is connected to the first selection control terminal MUX1, the first electrode is connected to the third source driving unit S3, and the second electrode is connected to the third source driving unit S3. It is connected to the data line D7 of the seventh column, and so on.

Wherein, the second selection circuit includes: P third transistors M3, the control electrode of the first third transistor M3 is connected to the second selection control terminal MUX2, and the first electrode thereof is connected to the first source driving unit S1, Its second pole is connected to the third column data line D3, the control pole of the second third transistor M3 is connected to the second selection control terminal MUX2, its first pole is connected to the second source driving unit S2, and its first pole is connected to the second source driving unit S2. The second electrode is connected to the fourth column data line D4, the control electrode of the third third transistor M3 is connected to the second selection control terminal MUX2, the first electrode is connected to the third source driving unit S3, and the second electrode is connected to the third source driving unit S3. It is connected to the data line D9 of the ninth column, and so on.

Wherein, the third selection circuit includes: P fourth transistors M4, the control electrode of the first fourth transistor M4 is connected to the third selection control terminal MUX3, and the first electrode thereof is connected to the first source driving unit S1, Its second pole is connected to the fifth column data line D5, the control pole of the second fourth transistor M4 is connected to the third selection control terminal MUX3, its first pole is connected to the second source driving unit S2, and its first pole is connected to the second source driving unit S2. The second electrode is connected to the sixth column data line D6, the control electrode of the third fourth transistor M4 is connected to the third selection control terminal MUX3, the first electrode is connected to the third source driving unit S3, and the second electrode is connected to the third source driving unit S3. It is connected to the data line D11 of the eleventh column, and so on.

In this embodiment, the transistors M1 to MQ+1 can all be N-type thin film transistors or P-type thin film transistors, so that the process flow can be unified, the process process can be reduced, and the yield of the product can be improved. In addition, considering that the leakage current of low temperature polysilicon thin film transistors is small, it is preferred that all transistors in the embodiments of the present application are low temperature polysilicon thin film transistors. The switch function can be realized.

The technical solutions of the embodiments of the present application are further described below through the working process of the display panel.

Taking the transistors M1 to M3 in the display panel provided in FIG. 5 as an example, all of which are N-type thin film transistors, FIG. 8 is a working timing diagram of the display panel provided in FIG. 5 , as shown in FIGS. 5 and 8 . The working process of the display panel specifically includes:

Now define a frame time as T, and the time in the first half of the frame includes: the first stage T1 and the second stage T2, specifically:

In the first stage T1, the input signal of the first selection control terminal MUX1 is at a high level, all the second transistors M2 are turned on, the input signal of the first scan line G1 is at a high level, and all the transistors connected to the first scan line G1 are at a high level. The first transistor M1 in the pixel unit is turned on. At this time, the first source driving unit S1 charges the red sub-pixels in the first row and the first column, and the second source driving unit S2 charges the red sub-pixels in the first row and the second column. The green sub-pixels are charged, and the third source driving unit S3 charges the green sub-pixels in the first row and the fifth column, and so on.

In the second stage T2, the input signal of the first selection control terminal MUX1 is low level, all the second transistors M2 are turned off, the input signal of the first scan line G1 is low level, and the pixel unit connected to the first scan line G1 The first transistor M1 is turned off, the first source driving unit S1 stops charging the red sub-pixels in the first row and the first column, and the second source driving unit S2 stops charging the green sub-pixels in the first row and the second column. Charging, the third source driving unit S3 stops charging the green sub-pixels in the first row and the fifth column, and so on. Due to the coupling effect of the storage capacitance of the first scan line G1, the pixel voltage will drop. At the same time, the input signal of the second selection control terminal MUX2 is high level, all the third transistors M3 are turned on, the input signal of the second row scan line G2 is high level, the first source driving unit S1 sends the first source driving unit S1 to the first The blue sub-pixels in the third row and the third column are charged, the second source driving unit S2 is charging the red sub-pixels in the first row and the fourth column, and the third source driving unit S3 is charging the red sub-pixels in the first row and the seventh column. The pixels are charged, and so on. At this time, the first row of pixel units are all lit.

After the second stage T2, the input signal of the second selection control terminal MUX2 is at a low level, the input signal of the second scan line G2 is at a low level, and the first transistor in the pixel unit connected to the second scan line G2 is at a low level. M1 is turned off, the first source driving unit S1 stops charging the blue sub-pixels in the first row and the third column, the second source driving unit S2 stops charging the red sub-pixels in the first row and the fourth column, and the third source driving unit S2 stops charging the red sub-pixels in the first row and the fourth column. The source driving units S3 stop charging the red sub-pixels in the first row and the seventh column, and so on. At this time, the pixel units that are charged in the second stage T2 will be subject to the second selection control terminal MUX2 and the second scan line. Due to the coupling effect of the G2 storage capacitor, the pixel voltage will drop.

Then, similar to the first stage T1 and the second stage T2, the third scan line G3 and the fourth scan line G4 are scanned successively. At this time, the pixel units of the third row are lit, and so on, until the first half frame time is T/ 2 is over, at this time, the entire screen presents a state in which odd-numbered rows of pixel units are on and even-numbered rows of pixel units are off, wherein.

At the beginning of the second half frame, namely T/2, it includes: the third stage T3, the fourth stage T4 and the fifth stage T5, specifically:

In the third stage T3, the input signals of the first selection control terminal MUX1 and the second selection control terminal MUX2 are both low level, the second transistor M2 and the third transistor M3 are turned off, and the input signal of the first scan line G1 is high. level, the first transistor M1 in the pixel unit connected to the first scan line G1 is turned on.

In the fourth stage T4, the input signal of the first selection control terminal MUX1 is at a high level, the second transistor M2 is turned on, and the input signal of the scan line G2 in the second row is at a high level. At this time, the first source drive The unit S1 charges the red sub-pixels in the second row and the first column, the second source driving unit S2 charges the green sub-pixels in the second row and the second column, and the third source driving unit S3 charges the second row and fifth sub-pixels. The green subpixels of the column are charged, and so on.

In the fifth stage T5, the input signal of the first selection control terminal MUX1 is low level, all the second transistors M2 are turned off, the input signal of the second scan line G2 is low level, and the pixel unit connected to the second scan line G2 The first transistor M1 is turned off, the first source driving unit S1 stops charging the red sub-pixels in the second row and the first column, and the second source driving unit S2 stops charging the green sub-pixels in the second row and the second column. Charging, the third source driving unit S3 stops charging the green sub-pixels in the second row and the fifth column, and so on. Due to the coupling effect of the storage capacitance of the second scan line G2, the pixel voltage will drop. At the same time, the input signal of the scan line G3 in the third row is at a high level, the first source driving unit S1 charges the blue sub-pixels in the second row and the third column, and the second source driving unit S2 charges the blue sub-pixels in the second row and the third column. The red sub-pixels in the fourth column are charged, and the third source driving unit S3 charges the red sub-pixels in the second row and the seventh column, and so on, and so on, the pixel units in the second row are all lit.

After the fifth stage T5, the input signal of the second selection control terminal MUX2 is low level, the input signal of the third row scan line G3 is low level, and the pixel unit connected to the third row scan line G3 is at a low level. When the transistor M1 is turned off, the first source driving unit S1 stops charging the blue sub-pixels in the second row and the third column, and the second source driving unit S2 stops charging the red sub-pixels in the second row and the fourth column. The third source driving unit S3 stops charging the red sub-pixels in the second row and seventh column, and so on. Due to the coupling effect of the stored capacitance of the scanning line G3, the pixel voltage will drop.

Then, similar to the fourth stage T4 and the second stage T5, the third scan line G3 and the fourth scan line G4 are scanned successively. At this time, the pixel units in the fourth row are lit, and so on, until the second half frame time is T/ 2 End, so that the pixels of the entire screen are all lit at the end of the frame.

In the working timing provided in Figure 8, each row of scan lines will be turned on twice in a frame time, the first scan line is turned on, the odd row pixels are turned on, the second scan line is turned on, and the even row pixels are turned on.

In the embodiment of the present application, under this timing operation, since the signals of the scan line and the selection control terminal drop at the same time, each pixel unit is only affected by coupling once after charging is completed, and the drop value of the pixel voltage of each pixel unit is the same. In this way, the difference in the charging rate of pixel units in adjacent columns is eliminated, thereby avoiding vertical stripes, and improving the display effect of the display panel.

Taking transistors M1 to M3 in the shift register provided in the display panel provided in FIG. 6 as an example, all of them are N-type thin film transistors, FIG. 9 is a working timing diagram of the display panel provided in FIG. 6 , as shown in FIGS. 6 and 9 . As shown, the working process of the display panel provided by the embodiment of the present application specifically includes:

In the first stage T1, the input signal of the first selection control terminal MUX1 is high level, all the second transistors M2 are turned on, the signal provided by the first scan line G1 is high level, and the pixels connected to the first scan line G1 The first transistor M1 in the unit is turned on. At this time, the first source driving unit S1 charges the red sub-pixels in the first row and the first column, and the second source driving unit S2 charges the red sub-pixels in the first row and the second column. The green sub-pixels are charged, and the third source driving unit S3 charges the green sub-pixels in the first row and the fifth column, and so on.

In the second stage T2, the input signal of the first selection control terminal MUX1 is low level, all the second transistors M2 are turned off, the input signal of the first scan line G1 is low level, and the pixel unit connected to the first scan line G1 The first transistor M1 is turned off, the first source driving unit S1 stops charging the red sub-pixels in the first row and the first column, and the second source driving unit S2 stops charging the green sub-pixels in the first row and the second column. Pixel charging, the third source driving unit S3 stops charging the green sub-pixels in the first row and the fifth column, and so on. Due to the coupling effect with the storage capacitance of the first scan line G1, the pixel voltage will drop. The input signal of the second selection control terminal MUX2 is high level, all the third transistors M3 are turned on, the input signal of the first sub-scan line G21 of the second row scan line G2 is high level, the first source drive The unit S1 charges the blue sub-pixels in the first row and the third column, the second source driving unit S2 charges the red sub-pixels in the first row and the fourth column, and the third source driving unit S3 charges the first row and the fourth column. The red sub-pixels in the seven columns are charged, and so on. At this time, the pixel units in the first row are all lit.

After the second stage T2, the input signal of the second selection control terminal MUX2 is at a low level, the input signal of the first sub-scanning line G21 of the second scanning line G2 is at a low level, and the input signal of the second scanning line G2 is at a low level. The first transistor M1 in the pixel unit connected to a sub-scan line G21 is turned off, the first source driving unit S1 stops charging the blue sub-pixels in the first row and the third column, and the second source driving unit S2 stops charging the blue sub-pixels in the first row and third column. The red sub-pixels in the first row and the fourth column are charged, and the third source driving unit S3 stops charging the red sub-pixels in the first row and the seventh column, and so on. At this time, the charging pixel unit is realized in the second stage T2 Affected by the coupling between the second selection control terminal MUX2 and the stored capacitance of the first sub-scan line G21 of the second scan line G2, the pixel voltage will decrease.

Then, similar to the first stage T1 and the second stage T2, the second sub-scanning line G22 of the second scanning line G2 and the first sub-scanning line G31 of the third scanning line G3 are successively scanned. Light up, and so on, so that at the end of a frame, all the pixels of the entire screen are lit up.

In the embodiment of the present application, under this timing operation, since the signals of the scan line and the selection control terminal drop at the same time, each pixel unit will only be affected by coupling once after the charging is completed, and the drop value of the pixel voltage of each pixel unit will be greatly reduced. In this way, the difference in the charging rate of pixel units in adjacent columns is eliminated, thereby avoiding vertical stripes, and improving the display effect of the display panel.

Based on the same inventive concept, some embodiments of the present application further provide a method for driving a display panel, which is used to drive the display panel of the foregoing embodiments. The driving method of the display panel provided by the embodiment of the present application includes: under the control of the selection control terminal, the multiplexing circuit inputs the data signal output by the source driving circuit into the corresponding data line in time division.

The driving method of the display panel provided by the embodiment of the present application is used to drive the display panel provided by the foregoing embodiment, and the implementation principle and effect thereof are similar and will not be repeated here.

Based on the same inventive concept, some embodiments of the present application further provide a display device, which includes: a display panel.

Optionally, the display device may be any product or component with a display function, such as an OLED panel, a mobile phone, a tablet computer, a TV, a monitor, a notebook computer, a digital photo frame, a navigator, etc., which is not limited in the embodiments of the present application. .

The display panel is the display panel provided in the foregoing embodiment, and its implementation principle and implementation effect are similar, and details are not described herein again.

The display device may include a display substrate, and the pixel circuit may be disposed on the display substrate. Preferably,

The drawings of the embodiments of the present invention only relate to the structures involved in the embodiments of the present invention, and other structures may refer to general designs.

Although the embodiments disclosed in the present invention are as above, the described contents are only the embodiments adopted to facilitate the understanding of the present invention, and are not intended to limit the present invention. Any person skilled in the art to which the present invention belongs, without departing from the spirit and scope disclosed by the present invention, can make any modifications and changes in the form and details of the implementation, but the scope of the patent protection of the present invention still needs to be The scope defined by the appended claims shall prevail.

Claims (10)

1. A display panel, characterized in that, comprising: M rows and N columns of pixel units, M+1 rows of scan lines, N columns of data lines, multiplexing circuits and source drive circuits; The i-th row of pixel units is connected to the i-th row scan line and the i+1-th row scan line respectively; the j-th column of pixel units is connected to the j-th column of data lines, 1≤i≤M, 1≤j≤N; The multiplex selection circuit is respectively connected with the selection control terminal, the source driving circuit and the N column data lines, and is used for inputting the data signal output by the source driving circuit to the corresponding data line in time-division under the control of the selection control terminal middle. 2 . The display panel according to claim 1 , wherein, for the pixel unit of the i-th row and the j-th column, when j=4k+1 or 4k+2, the i-th row and the j-th column of the pixel unit and the i-th row scan line connection; When j=4k+3 or 4k+4, the pixel unit in the i-th row and the j-th column is connected to the scan line in the i+1-th row, where 0≤k<N/4. 3 . The display panel according to claim 1 , wherein the scan line in the s-th row comprises: a first sub-scan line and a second sub-scan line, 1<s≦M; 3 . The first sub-scan line of the scan line in the s-th row is connected to the pixel unit in the s-1-th row and the t1-th column, where t1=4k+3 or 4k+4, 0≤k<N/4; The second sub-scan line of the s-th row scan line is connected to the s-th row and the t2-th column pixel unit, wherein t2=4k+1 or 4k+2; The scan line of the first row is connected to the pixel unit of the first row and the t2th column, and the scan line of the M+1th row is connected to the pixel unit of the Mth row and the t1th column. 4. The display panel according to claim 2 or 3, wherein, for the pixel unit in the i-th row and the j-th column, the pixel unit comprises: a display element and a switch element, and the switch element comprises: a first transistor; When j=4k+1 or 4k+2, the control electrode of the first transistor is connected to the scan line of the i-th row, the first electrode of the first transistor is connected to the data line of the j-th column, and the second electrode of the first transistor is connected to the display line component connection; When j=4k+3 or 4k+4, the control electrode of the first transistor is connected to the scan line of the i+1th row, the first electrode of the first transistor is connected to the data line of the jth column, and the second electrode of the first transistor is connected to the scan line of the i+1th row. Connect with the display element. 5 . The display panel according to claim 4 , wherein the source driving circuit comprises: P source driving units, the multiplexing circuit comprises: Q selection circuits, and the selection control terminal comprises: 6 . : Q selection control terminals, the selection control terminals are in one-to-one correspondence with the selection circuit, where P×Q=N; The i-th selection circuit is respectively connected to the corresponding selection control terminal, the P source driving units, the 2Qk+2i-1th column data line and the 2Qk+2i-th column data line, where 1≤i≤Q, 0≤ k<N/2Q. 6. The display panel according to claim 5, wherein the ith selection circuit comprises: P ith+1 transistors; The control pole of the jth i+1th transistor is connected to the selection control terminal corresponding to the ith selection circuit, and the first pole of the jth i+1th transistor is connected to the jth source driving unit; When j is an even number, the second pole of the jth i+1th transistor is connected to the data line of the (j-2)Q+2ith column, and when j is an odd number, the second pole of the jth i+1th transistor The pole is connected to the data line of the (j-1)th Q+2i-1 column, 1≤j≤P. 7 . The display panel according to claim 1 , wherein the electrical signals on the adjacent plurality of data lines are arranged in sequence according to the order of positive polarity and negative polarity. 8 . 8 . The display panel of claim 1 , wherein the multiplexing circuit and the source driving circuit are located in a non-display area of the display panel. 9 . 9. A display device, comprising: the display panel according to any one of claims 1 to 8. 10. A method for driving a display panel, wherein the method is used for driving the display panel according to any one of claims 1 to 8, the method comprising: Under the control of the selection control terminal, the multiplex selection circuit time-divisions and inputs the data signal output by the source driver circuit into the corresponding data line.