CN108717187A - Based on multinuclear digital signal processor through-wall radar motion target tracking imaging method - Google Patents
Based on multinuclear digital signal processor through-wall radar motion target tracking imaging method Download PDFInfo
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Abstract
一种基于多核数字信号处理器穿墙雷达运动目标跟踪成像方法,涉及数字信号处理技术领域,解决的问题是满足超宽带雷达成像实时性要求,具体步骤如下:(1)对移动目标进行信息数据采集并输入PC端;(2)将信息数据进行数据封装并传至多核数字信号处理器进行处理;(3)将数据分为8份,存入公共存储区;(4)以Core0作为主核,控制系统的初始化,通知其他从核执行各自任务;(5)以Core1‑7作为从核,访问公共存储区的数据;(6)每一个核读取信息数据并进行时延计算,将结果送至原有存储区;(7)主核Core0进行最后算法的叠加整理,并原路送回至PC端。本发明运算效率高,满足了运动目标跟踪成像的实时性要求。
A moving target tracking and imaging method based on a multi-core digital signal processor through-wall radar, which involves the field of digital signal processing technology, and solves the problem of meeting the real-time requirements of ultra-wideband radar imaging. The specific steps are as follows: Collect and input to the PC; (2) Encapsulate the information data and transmit it to the multi-core digital signal processor for processing; (3) Divide the data into 8 parts and store them in the public storage area; (4) Use Core0 as the main core , control the initialization of the system, and notify other slave cores to perform their respective tasks; (5) use Core1-7 as the slave core to access the data in the public storage area; (6) each core reads the information data and performs delay calculation, and the result Send it to the original storage area; (7) The main core Core0 performs the superposition and sorting of the final algorithm, and sends it back to the PC side through the original route. The invention has high computing efficiency and meets the real-time requirement of moving target tracking and imaging.
Description
技术领域technical field
本发明涉及数字信号处理技术领域,具体涉及一种基于多核数字信号处理器穿墙雷达运动目标跟踪成像方法。The invention relates to the technical field of digital signal processing, in particular to a method for tracking and imaging a moving target based on a multi-core digital signal processor through-wall radar.
背景技术Background technique
随着科技生活的飞跃式发展,根据军事、保卫国民身体财产安全以及一些商业要求,雷达作为一种可以探测目标、跟踪成像的高端技术已经成为了各大研究机构和商业公司争先恐后所要研究的重要课题。当面对地质勘探、灾后救援、恐怖组织袭击时,超宽带(UWB)穿墙探测技术凭借其特有的强穿透性、极高的距离分辨率、清晰的成像结果等特点,在近距离探测场景中有着广泛的应用。With the rapid development of scientific and technological life, according to the requirements of the military, the protection of national physical and property safety, and some commercial requirements, radar, as a high-end technology that can detect targets and track and image, has become an important research institute and commercial company. topic. When faced with geological exploration, post-disaster rescue, and terrorist organization attacks, ultra-wideband (UWB) wall-penetrating detection technology relies on its unique strong penetrability, high distance resolution, and clear imaging results. There are a wide range of applications in the scene.
随着数字信号处理技术地不断发展,目标识别与定位对超宽带雷达成像技术实现提出了高分辨率、强实时性的要求,使得超宽带雷达成像系统能够处理海量数据、完成复杂的成像的算法,具有更高的数据吞吐能力。传统的雷达信号处理系统平台使用的是单核处理器,设备结构复杂,功能简单,难以满足高速处理的实时信号的要求。多核在这种情况下应运而生,多核相比单核,拥有更快的处理性能,占用更小的PCB面积,更低的功耗,成为了近些年数字信号处理器中的佼佼者。With the continuous development of digital signal processing technology, target recognition and positioning put forward high-resolution and strong real-time requirements for the realization of ultra-wideband radar imaging technology, so that the ultra-wideband radar imaging system can process massive data and complete complex imaging algorithms , with higher data throughput. The traditional radar signal processing system platform uses a single-core processor, which has a complex structure and simple functions, and it is difficult to meet the requirements of high-speed processing of real-time signals. In this case, multi-core came into being. Compared with single-core, multi-core has faster processing performance, occupies a smaller PCB area, and lower power consumption. It has become a leader in digital signal processors in recent years.
穿墙成像雷达的特点是信号复杂度高、数据量巨大、处理实时性较难实现。就目前而言,硬件实现技术主要有现场可编程门阵列(field programmable gate array,简称FPGA)技术、专业ASIC(application specific integrated circuits)芯片技术技术二大类。FPGA普遍用来实现数字电路模块,拥有丰富的逻辑资源、I/O资源,适用于框图式编程、任务比较固定或者重复的情况下的场合,在信号处理的场景下主要利用自身的优势用来负责接口控制,完成较低复杂度的算法,一般普遍用于雷达信号的采集部分。专业ASIC芯片技术拥有较高的速度和尽可能小的面积以及完全满意的封装,但是其灵活较差,设计成本昂贵。Through-wall imaging radar is characterized by high signal complexity, huge data volume, and difficult real-time processing. For now, hardware implementation technologies mainly include field programmable gate array (field programmable gate array, FPGA for short) technology and professional ASIC (application specific integrated circuits) chip technology. FPGA is generally used to implement digital circuit modules, and has rich logic resources and I/O resources. It is suitable for block diagram programming, fixed or repetitive tasks, and mainly uses its own advantages in signal processing scenarios. It is responsible for interface control and completes algorithms with relatively low complexity. It is generally used in the acquisition part of radar signals. Professional ASIC chip technology has high speed, the smallest possible area and a fully satisfactory package, but its flexibility is poor and the design cost is expensive.
发明内容Contents of the invention
针对现有技术的不足,本发明所解决的问题是满足超宽带雷达成像实时性要求。Aiming at the deficiencies of the prior art, the problem solved by the invention is to meet the real-time requirement of ultra-wideband radar imaging.
为解决上述技术问题,本发明采用的技术方案是一种基于多核数字信号处理器穿墙雷达运动目标跟踪成像方法,具体步骤如下:In order to solve the above-mentioned technical problems, the technical solution adopted in the present invention is a method for tracking and imaging moving targets based on multi-core digital signal processor through-wall radar, and the specific steps are as follows:
(1)利用雷达信号采集设备对墙后移动目标进行信息数据采集输入PC端;(1) Use the radar signal acquisition equipment to collect information and data of the moving target behind the wall and input it to the PC;
(2)PC端将所获取的移动目标的信息数据按时间间隔进行数据封装,依次通过千兆以太网传输至多核数字信号处理器进行处理,优选地,所述时间间隔为0.01秒;(2) The PC side encapsulates the acquired information data of the moving target according to time intervals, and sequentially transmits them to the multi-core digital signal processor through Gigabit Ethernet for processing. Preferably, the time interval is 0.01 seconds;
(3)多核数字信号处理器将所接受的数据分为8份,存入公共存储区;(3) The multi-core digital signal processor divides the received data into 8 parts and stores them in the public storage area;
(4)以Core0作为主核,控制系统的初始化,通过IPC核间通信通知其他从核执行各自任务;(4) Take Core0 as the main core, control the initialization of the system, and notify other slave cores to perform their respective tasks through IPC inter-core communication;
(5)以Core1-7作为从核,接受到主核Core0命令后,访问公共存储区的数据,按照存储地址读取各自需要的原始数据;(5) With Core1-7 as the slave core, after receiving the command from the master core Core0, access the data in the public storage area, and read the original data they need according to the storage address;
(6)每一个核读取对应的通道信息数据,按照雷达BP成像算法进行时延计算,计算完成后将所得结果送至原有存储区;(6) Each core reads the corresponding channel information data, performs time delay calculation according to the radar BP imaging algorithm, and sends the result to the original storage area after the calculation is completed;
(7)主核Core0将每一个核的结果进行最后算法的叠加整理,并将结果通过千兆以太网原路送回至PC端。(7) The main core Core0 performs the superposition and sorting of the results of each core in the final algorithm, and sends the results back to the PC through the original Gigabit Ethernet.
步骤(2)、步骤(7)中,所述千兆以太网利用NDK(Network Development Kit)网络开发套件,通过底层硬件驱动程序设计以TCP/IP协议创建网络端口、IP绑定和任务进程,采用用户端的网络应用程序设计,通过TCP网络,按照网络协议将需要处理的数据发送给多核数字信号处理器的服务器,多核数字信号处理器接收到数据后进行运算,运算结束后将运算结果,再发送给客户端,完成数据之间的交互;In step (2) and step (7), the Gigabit Ethernet utilizes the NDK (Network Development Kit) network development kit to create network ports, IP bindings and task processes with the TCP/IP protocol through the underlying hardware driver design, The network application program design of the client is adopted, and the data to be processed is sent to the server of the multi-core digital signal processor through the TCP network according to the network protocol. Send to the client to complete the interaction between data;
所述底层硬件驱动程序采用硬件信号量来进行互斥,根据自己的需求使用相应的驱动函数,进行参数配置修改;The underlying hardware driver program uses hardware semaphores to perform mutual exclusion, and uses corresponding driver functions according to its own needs to modify parameter configurations;
所述TCP/IP协议采用TCP协议;The TCP/IP protocol adopts the TCP protocol;
所述用户端的网络应用程序采用套接字socket开发服务器,包括以下过程;The network application program of described user end adopts socket socket development server, comprises following process;
1)创建socket服务器对象,监听套接字;1) Create a socket server object and listen to the socket;
2)建立连接,并等待客户端发起主动连接请求;2) Establish a connection and wait for the client to initiate an active connection request;
3)发送接收数据,服务器端则负责监听连接请求,请求通过后开始传输数据;3) Send and receive data, and the server is responsible for monitoring the connection request, and starts to transmit data after the request is passed;
4)关闭文件对话,断开连接。4) Close the file dialog and disconnect.
步骤(4)中,利用多核数字信号处理器的并行架构的特点,将计算的数据按照通道数划分,计算每一个通道的信息数据,最后做一个叠加运算;In step (4), utilizing the characteristics of the parallel architecture of the multi-core digital signal processor, the calculated data is divided according to the number of channels, the information data of each channel is calculated, and finally a superposition operation is performed;
步骤(6)中,多核数字信号处理器根据任务的分配选择主从拓扑结构,利用IPC中断作为通信方式,Core0作为主核单元与外界进行数据交换,并通过核间中断与从核进行数据通信和状态同步,通过主核的中断触发执行任务,从核进行算法计算任务;In step (6), the multi-core digital signal processor selects the master-slave topology according to the assignment of tasks, uses IPC interrupts as the communication method, Core0 acts as the master core unit to exchange data with the outside world, and communicates with the slave cores through inter-core interrupts Synchronized with the state, the execution task is triggered by the interrupt of the master core, and the algorithm calculation task is performed by the slave core;
本发明的有益效果:实现了PC端与多核数字信号处理器之间的数据传输,根据主从模型对雷达BP成像算法进行任务规划,调用多核同步执行计算任务,提高了运算效率,实现运动目标跟踪成像的实时性。Beneficial effects of the present invention: realize the data transmission between the PC end and the multi-core digital signal processor, carry out task planning on the radar BP imaging algorithm according to the master-slave model, call the multi-core synchronously to execute calculation tasks, improve the calculation efficiency, and realize the moving target Real-time tracking imaging.
附图说明Description of drawings
图1为本发明方法流程图;Fig. 1 is a flow chart of the method of the present invention;
图2为本发明以太网程序设计的流程示意图;Fig. 2 is the schematic flow chart of Ethernet program design of the present invention;
图3为本发明中雷达BP成像算法的流程图;Fig. 3 is the flowchart of radar BP imaging algorithm among the present invention;
图4为本发明并行架构设计的主从模型。Fig. 4 is the master-slave model of the parallel architecture design of the present invention.
具体实施方式Detailed ways
下面结合附图和实施例对本发明的具体实施方式作进一步的说明,但不是对本发明的限定。The specific implementation manners of the present invention will be further described below in conjunction with the drawings and examples, but the present invention is not limited.
实施例:选用TI公司的TMS320C6678多核数字信号处理器来进行说明。Embodiment: select TMS320C6678 multi-core digital signal processor of TI Company to illustrate.
在本实施例中,如图1所示,将每一个通道的数据量划分为一个基本任务数据量,计算的数据量可划分为n个基本任务,n取决于雷达采集通道的数量。In this embodiment, as shown in FIG. 1 , the data volume of each channel is divided into a basic task data volume, and the calculated data volume can be divided into n basic tasks, where n depends on the number of radar acquisition channels.
图1示出了一种基于多核数字信号处理器穿墙雷达运动目标跟踪成像方法,具体步骤如下:Figure 1 shows a method for tracking and imaging moving targets based on multi-core digital signal processor through-wall radar, and the specific steps are as follows:
(1)利用雷达信号采集设备对墙后移动目标进行信息数据采集输入PC端;(1) Use the radar signal acquisition equipment to collect information and data of the moving target behind the wall and input it to the PC;
(2)PC端将所获取的移动目标的信息数据按时间间隔进行数据封装,依次通过千兆以太网传输至多核数字信号处理器进行处理,优选地,所述时间间隔为0.01秒;(2) The PC side encapsulates the acquired information data of the moving target according to time intervals, and sequentially transmits them to the multi-core digital signal processor through Gigabit Ethernet for processing. Preferably, the time interval is 0.01 second;
(3)多核数字信号处理器将所接受的数据分为8份,存入公共存储区;(3) The multi-core digital signal processor divides the received data into 8 parts and stores them in the public storage area;
(4)以Core0作为主核,控制系统的初始化,通过IPC核间通信通知其他从核执行各自任务;(4) Take Core0 as the main core, control the initialization of the system, and notify other slave cores to perform their respective tasks through IPC inter-core communication;
(5)以Core1-7作为从核,接受到主核Core0命令后,访问公共存储区的数据,按照存储地址读取各自需要的原始数据;(5) With Core1-7 as the slave core, after receiving the command from the master core Core0, access the data in the public storage area, and read the original data they need according to the storage address;
(6)每一个核读取对应的通道信息数据,按照雷达BP成像算法进行时延计算,计算完成后将所得结果送至原有存储区;(6) Each core reads the corresponding channel information data, performs time delay calculation according to the radar BP imaging algorithm, and sends the result to the original storage area after the calculation is completed;
(7)主核Core0将每一个核的结果进行最后算法的叠加整理,并将结果通过千兆以太网原路送回至PC端。(7) The main core Core0 performs the superposition and sorting of the final algorithm on the results of each core, and sends the results back to the PC through the original Gigabit Ethernet.
步骤(2)、步骤(7)中,所述千兆以太网利用NDK(Network Development Kit)网络开发套件,通过底层硬件驱动程序设计、以TCP/IP协议创建网络端口、IP绑定和任务进程,采用用户端的网络应用程序设计,通过TCP网络,按照网络协议将需要处理的数据发送给多核数字信号处理器的服务器,多核数字信号处理器接收到数据后进行运算,运算结束后将运算结果,再发送给客户端,完成数据之间的交互;In step (2) and step (7), the Gigabit Ethernet utilizes the NDK (Network Development Kit) network development kit to create a network port, IP binding and task process through the underlying hardware driver design and TCP/IP protocol , using the network application design of the client, through the TCP network, according to the network protocol, the data to be processed is sent to the server of the multi-core digital signal processor, the multi-core digital signal processor performs calculation after receiving the data, and after the calculation is completed, the calculation result, Then send it to the client to complete the interaction between data;
所述底层硬件驱动程序采用硬件信号量来进行互斥,根据自己的需求使用相应的驱动函数,进行参数配置修改;The underlying hardware driver program uses hardware semaphores to perform mutual exclusion, and uses corresponding driver functions according to its own needs to modify parameter configurations;
所述TCP/IP协议采用TCP协议;The TCP/IP protocol adopts the TCP protocol;
所述用户端的网络应用程序采用套接字socket开发服务器,包括以下过程,如图2所示;The network application program of described user end adopts socket socket development server, comprises following process, as shown in Figure 2;
1)创建socket服务器对象,监听套接字;1) Create a socket server object and listen to the socket;
2)建立连接,并等待客户端发起主动连接请求;2) Establish a connection and wait for the client to initiate an active connection request;
3)发送接收数据,服务器端则负责监听连接请求,请求通过后开始传输数据;3) Send and receive data, and the server is responsible for monitoring the connection request, and starts to transmit data after the request is passed;
4)关闭文件对话,断开连接。4) Close the file dialog and disconnect.
在本实施例中,选择静态IP(StaticIP)模式编程指定TMS320C6678的IP地址。多核数字信号处理器的IP地址:192.168.2.100,PC端的IP地址:192.168.2.102。C6678网口和PC端之间是通过100Mbps网卡模式的方式连接,PC端与C6678 的IP端口握手协议达成后网络通路建立,开始传输数据。由于初始化程序需要在核0上完成,因此将核0选作实现网络通信的控制核,核0与其他核的数据交换在公共存储区上完成。In this embodiment, select the static IP (StaticIP) mode to program and specify the IP address of TMS320C6678. The IP address of the multi-core digital signal processor: 192.168.2.100, the IP address of the PC: 192.168.2.102. The C6678 network port and the PC are connected through a 100Mbps network card mode. After the handshake agreement between the PC and the C6678's IP port is reached, the network path is established and data transmission begins. Since the initialization program needs to be completed on core 0, core 0 is selected as the control core for network communication, and the data exchange between core 0 and other cores is completed on the public storage area.
步骤(4)中, 如图3所示,利用多核数字信号处理器的并行架构的特点,将计算的数据按照通道数划分,计算每一个通道的信息数据,最后做一个叠加运算;In step (4), as shown in Figure 3, utilize the characteristics of the parallel architecture of the multi-core digital signal processor to divide the calculated data according to the number of channels, calculate the information data of each channel, and finally perform a superposition operation;
在本实施例中,所述多核数字信号处理器的并行架构采用主从模型,如图4所示,主核核0为主控制核,负责系统的初始化,对数据进行初步操作,核1-7作为从属核,接收核0的指令进行相关运算,并将所得结果传送给核0做最后的数据整合。In this embodiment, the parallel architecture of the multi-core digital signal processor adopts a master-slave model. As shown in FIG. 7, as a slave core, receives instructions from core 0 to perform related operations, and sends the result to core 0 for final data integration.
步骤(6)中,多核数字信号处理器根据任务的分配选择主从拓扑结构,利用IPC中断作为通信方式,Core0作为主核单元与外界进行数据交换,并通过核间中断与从核进行数据通信和状态同步,通过主核的中断触发执行任务,从核进行算法计算任务;In step (6), the multi-core digital signal processor selects the master-slave topology according to the assignment of tasks, uses IPC interrupts as the communication method, Core0 acts as the master core unit to exchange data with the outside world, and communicates with the slave cores through inter-core interrupts Synchronized with the state, the execution task is triggered by the interrupt of the master core, and the algorithm calculation task is performed by the slave core;
在本实施例中,在目标运动中,对运动目标轨迹进行追踪。以运动目标开始的时间为基准,以0.2秒的间隔对目标进行成像,以每秒6帧的帧率分别在目标运动的第0秒,0.2秒,0.4秒,0.6秒,0.8秒,1秒的时刻对目标进行成像。对每帧图像数据作为一个文件依次输入,在多核数字信号处理器中对其进行依次处理,将所得处理结果进行最后叠加就可以得到运动目标的运动轨迹,从而对目标运动方向和距离进行判断。In this embodiment, during the movement of the target, the trajectory of the moving target is tracked. Taking the start time of the moving target as the benchmark, the target is imaged at intervals of 0.2 seconds, and the frame rate is 6 frames per second at the 0th second, 0.2 second, 0.4 second, 0.6 second, 0.8 second, and 1 second of the target movement time to image the target. Each frame of image data is sequentially input as a file, processed sequentially in the multi-core digital signal processor, and the obtained processing results are finally superimposed to obtain the moving track of the moving target, so as to judge the moving direction and distance of the target.
以上结合附图对本发明的实施方式做出了详细说明,但本发明不局限于所描述的实施方式。对于本领域技术人员而言,在不脱离本发明的原理和精神的情况下,对这些实施方式进行各种变化、修改、替换和变型仍落入本发明的保护范围内。The embodiments of the present invention have been described in detail above with reference to the accompanying drawings, but the present invention is not limited to the described embodiments. For those skilled in the art, without departing from the principle and spirit of the present invention, various changes, modifications, replacements and modifications to these embodiments still fall within the protection scope of the present invention.
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