CN104155821B - TFT array substrate and driving method thereof, display panel and display device - Google Patents

Abstract

The invention discloses a TFT array substrate, a driving method, a display panel and a display device, wherein the TFT array substrate comprises: a plurality of data lines; first-Nth gate line units, each gate line unit including a first gate line and a second gate line; and a pixel region including first to N +2 th rows of pixels; the first gate line of the ith-level gate line unit drives a plurality of pixels of the ith row of pixels, the second gate line of the ith-level gate line unit drives a plurality of pixels of the (i + 2) th row of pixels, the plurality of pixels driven by the first gate line of the ith-level gate line unit and the plurality of pixels driven by the second gate line of the ith-level gate line unit are alternately arranged in spatial position, 1< i > N, and N is an integer. The TFT array substrate is driven in a mode of conforming to dot inversion, so that the cross talk phenomenon is improved, and the image display effect is improved.

Description

TFT array substrate and driving method thereof, display panel and display device

technical field

The present invention relates to the field of display technology, and more specifically, to a TFT (Thin Film Transistor, Thin Film Field Effect Transistor) array substrate, a driving method, a display panel and a display device.

Background technique

Liquid crystal display devices have the advantages of light and thin appearance, low power consumption, and no radiation pollution, and have been widely used in electronic products such as computers, personal digital assistants, and mobile phones. The driving methods of existing liquid crystal display devices include: frame inversion (Frame Inversion) method, line inversion (Line Inversion) method and point inversion (Dot Inversion) method, and the liquid crystal display with the dot inversion method as the driving method The device improves the crosstalk phenomenon and improves the display effect. Wherein, the dot inversion mode is that the voltage polarity of each pixel unit is opposite to that of four adjacent pixel units in the horizontal direction and the vertical direction.

Contents of the invention

In view of this, the present invention provides a TFT array substrate, a driving method, a display panel and a display device. By driving the TFT array substrate to realize a dot inversion mode, the crosstalk phenomenon is improved, and the display image effect is improved.

The technical solutions provided by the invention include:

A TFT array substrate, comprising:

Multiple data lines for transmitting data signals;

The first level gate line unit to the Nth level gate line unit are used to transmit gate driving signals, each gate line unit includes a first gate line and a second gate line, and any gate line unit The first gate line and the second gate line transmit the gate driving signal at the same time;

And, a pixel area including the first row of pixels to the N+2th row of pixels;

Wherein, the first gate line of the i-level gate line unit is used to drive a plurality of pixels in the i-th row of pixels, and the second gate line of the i-level gate line unit is used to drive the i+2th row A plurality of pixels of the pixel, and the plurality of pixels driven by the first gate line of the i-level gate line unit and the plurality of pixels driven by the second gate line of the i-level gate line unit are spaced The positions are arranged alternately, 1<=i<=N, where N is an integer.

A driving method for driving a TFT array substrate, the TFT array substrate comprising: a plurality of data lines for transmitting data signals;

The first level gate line unit to the Nth level gate line unit are used to transmit gate driving signals, each gate line unit includes a first gate line and a second gate line, and any gate line unit The first gate line and the second gate line transmit the gate driving signal at the same time;

And, a pixel area including the first row of pixels to the N+2th row of pixels;

Wherein, the first gate line of the i-level gate line unit is used to drive a plurality of pixels in the i-th row of pixels, and the second gate line of the i-level gate line unit is used to drive the i+2th row A plurality of pixels of the pixel, and the plurality of pixels driven by the first gate line of the i-level gate line unit and the plurality of pixels driven by the second gate line of the i-level gate line unit are spaced The positions are alternately arranged, 1<=i<=N, N is an integer;

The driving method includes:

Carry out step-by-step scanning along the first-level gate line unit to the N-th level gate line unit, and transmit data signals through the plurality of data lines, wherein, after scanning the i-th level gate line unit, every scan In the two-stage gate line unit, the polarities of the data signals of the plurality of data lines are reversed.

A display panel comprising a TFT array substrate, the TFT array substrate comprising: a plurality of data lines for transmitting data signals;

The first level gate line unit to the Nth level gate line unit are used to transmit gate driving signals, each gate line unit includes a first gate line and a second gate line, and any gate line unit The first gate line and the second gate line transmit the gate driving signal at the same time;

And, a pixel area including the first row of pixels to the N+2th row of pixels;

Wherein, the first gate line of the i-level gate line unit is used to drive a plurality of pixels in the i-th row of pixels, and the second gate line of the i-level gate line unit is used to drive the i+2th row A plurality of pixels of the pixel, and the plurality of pixels driven by the first gate line of the i-level gate line unit and the plurality of pixels driven by the second gate line of the i-level gate line unit are spaced The positions are arranged alternately, 1<=i<=N, where N is an integer.

A display device, including a display panel, the display panel includes a TFT array substrate, and the TFT array substrate includes: a plurality of data lines for transmitting data signals;

The first level gate line unit to the Nth level gate line unit are used to transmit gate driving signals, each gate line unit includes a first gate line and a second gate line, and any gate line unit The first gate line and the second gate line transmit the gate driving signal at the same time;

And, a pixel area including the first row of pixels to the N+2th row of pixels;

Wherein, the first gate line of the i-level gate line unit is used to drive a plurality of pixels in the i-th row of pixels, and the second gate line of the i-level gate line unit is used to drive the i+2th row A plurality of pixels of the pixel, and the plurality of pixels driven by the first gate line of the i-level gate line unit and the plurality of pixels driven by the second gate line of the i-level gate line unit are spaced The positions are arranged alternately, 1<=i<=N, where N is an integer.

Compared with the prior art, the technical solution provided by the invention has the following advantages:

The invention provides a TFT array substrate, a driving method, a display panel, and a display device. The TFT array substrate includes: a plurality of data lines for transmitting data signals; a first-level gate line unit to an N-th level gate line unit , used to transmit the gate drive signal, each gate line unit includes a first gate line and a second gate line, and the first gate line and the second gate line of any gate line unit transmit the gate at the same time a pole driving signal; and, a pixel area including the first row of pixels to the N+2th row of pixels; wherein, the first gate line of the i-th gate line unit is used to drive a plurality of pixels of the i-th row of pixels, The second gate line of the i-level gate line unit is used to drive a plurality of pixels in the i+2 row of pixels, and the plurality of pixels driven by the first gate line of the i-level gate line unit are the same as those of the i-level A plurality of pixels driven by the second gate line of the gate line unit are alternately arranged in spatial positions, 1<=i<=N, where N is an integer.

It can be seen from the above content that when scanning step by step along the gate line unit of the first level to the gate line unit of the Nth level, multiple data lines transmit data signals at the same time, wherein, when scanning the gate line unit of the i level Afterwards, the polarities of the data signals of the multiple data lines are reversed every time two gate line units are scanned. Drive the TFT array substrate by the above method, and then realize the pixel units of two adjacent pixels with the same voltage polarity in each column of pixels, and the dot inversion mode in which the polarity of the pixel units in the horizontal direction and the vertical direction is opposite, improving the The phenomenon of crosstalk improves the display image effect.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only It is an embodiment of the present invention, and those skilled in the art can also obtain other drawings according to the provided drawings without creative work.

Figure 1a is a schematic diagram of a TFT array substrate capable of realizing dot inversion provided by an embodiment of the present application;

FIG. 1b is a schematic diagram of another TFT array substrate capable of realizing dot inversion provided by the embodiment of the present application;

Fig. 2a is a schematic diagram of another TFT array substrate capable of realizing dot inversion provided by the embodiment of the present application;

Fig. 2b is a schematic diagram of another TFT array substrate capable of realizing dot inversion provided by the embodiment of the present application;

Fig. 3a is a schematic diagram of pixel polarity distribution when driving a TFT array substrate provided by the embodiment of the present application;

Fig. 3b is a schematic diagram of pixel polarity distribution when driving another TFT array substrate provided by the embodiment of the present application;

Fig. 3c is a schematic diagram of pixel polarity distribution when driving another TFT array substrate provided by the embodiment of the present application;

FIG. 4 is a schematic diagram of another TFT array substrate capable of realizing dot inversion provided by the embodiment of the present application;

Fig. 5a is a schematic diagram of an arrangement mode between gate line units provided by an embodiment of the present application;

FIG. 5b is a schematic diagram of another arrangement of gate line units provided by the embodiment of the present application;

FIG. 5c is a schematic diagram of another arrangement of gate line units provided by the embodiment of the present application;

FIG. 6 is a schematic structural diagram of a TFT array substrate provided in an embodiment of the present application;

FIG. 7 is a schematic structural diagram of a display device provided by an embodiment of the present application.

Detailed ways

The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

As mentioned in the background art, using the dot inversion method to drive the liquid crystal display device can improve the crosstalk phenomenon and improve the display image effect, so the dot inversion method has become the focus of current research.

Based on this, the present application provides a TFT array substrate capable of realizing double-point inversion. The technical solution provided by the present application will be described in detail with reference to FIGS. 1a-2b.

Among them, the TFT array substrate includes:

A plurality of data lines (D1-Dm) are used to transmit data signals, and the plurality of data lines (D1-Dm) are all electrically connected to the source drive circuit 100, and the data signals are transmitted through the control of the source drive circuit 100;

The first level gate line unit G1 to the Nth level gate line unit Gn are used to transmit gate driving signals, and each gate line unit is electrically connected to the gate driving circuit 200, through the gate driving circuit 200 Controlling the transmission of gate drive signals, each gate line unit includes a first gate line and a second gate line, and the first gate line and the second gate line of any gate line unit transmit the gate drive at the same time signal, that is, the first gate line and the second gate line of any gate line unit are electrically connected, and simultaneously transmit a gate drive signal of the same polarity;

And, a pixel area including the first row of pixels P1 to the N+2th row of pixels Pn+2;

Wherein, the first gate line Gi1 of the i-level gate line unit Gi is used to drive a plurality of pixels P100 in the i-th row of pixels Pi, and the second gate line Gi2 of the i-level gate line unit Gi is used to drive the i-th row of pixels Pi. A plurality of pixels P200 in the i+2 row of pixels Pi+2, and a plurality of pixels P100 driven by the first gate line Gi1 of the i-level gate line unit Gi and the second gate of the i-level gate line unit Gi A plurality of pixels P200 driven by the line Gi2 are alternately arranged in spatial positions, 1<=i<=N, where N is an integer.

In the above content, the plurality of pixels P100 driven by the first gate line Gi1 of the i-level gate line unit Gi and the plurality of pixels P200 driven by the second gate line Gi2 of the i-level gate line unit Gi Arranged alternately in space. Its spatial position, that is, in the direction X parallel to the i-th row of pixels Pi, the plurality of pixels P100 driven by the first gate line Gi1 of the i-th gate line unit Gi and the first gate line unit Gi of the i-th level gate line unit Gi A plurality of pixels P200 driven by two gate lines Gi2 are arranged alternately. In addition, the multiple rows of pixels and the multi-level gate line units provided by the embodiment of the present application are all arranged along the direction Y, and the multiple data lines are arranged along the direction X (along the direction parallel to the i-th row of pixels).

The arrangement of the pixel regions on the TFT array substrate provided by the embodiment of the present application will be further described below. In the actual application of the display device, since the uniformity of the display screen of the display device is required, the arrangement of the pixels in the pixel region is uniform, and neat. Therefore, according to the above-mentioned arrangement of driving pixels in the i-th gate line unit, the finally obtained pixel area not only includes the first row of pixels to the N+2th row of pixels, but also passes through the first row of pixels to the Nth row of pixels. +2 rows of pixels form multiple columns of pixel columns. Therefore, in the odd-numbered position and the even-numbered position described in the embodiment of the present application, that is, along the direction parallel to the i-th row of pixels, any end of the plurality of pixel columns formed is selected as the first pixel column, that is, the odd-numbered position; and the next The pixel row is at an even position, and the subsequent pixel row is alternately at an odd position and an even position.

It should be noted that, in the TFT array substrate shown in Figures 1a to 2b provided by the embodiment of the present application, in the direction X parallel to the i-th row of pixels Gi, multiple rows of pixels selected and formed are located in the direction of the data line D1 The end of is the first column, which is the odd position.

Referring to FIG. 1 a , it is a schematic diagram of a TFT array substrate capable of realizing dot inversion provided by an embodiment of the present application, wherein the first gate line Gi1 of the i-th gate line unit Gi is electrically connected to the i-th gate line unit Gi1. A plurality of pixels P100 in the odd-numbered positions of the row of pixels Pi, and a plurality of pixels P200 in the even-numbered positions of the i+2th row of pixels Pi+2 are electrically connected to the second gate line Gi2 of the i-th gate line unit Gi ;or,

In other embodiments of the present application, it can also be distributed in another arrangement. Specifically, refer to FIG. The first gate line Gi1 of the level gate line unit Gi is electrically connected to a plurality of pixels P100 in the even position of the i-th row of pixels Pi, and the second gate line Gi2 of the i-level gate line unit Gi is electrically connected to A plurality of pixels P200 at odd positions of the i+2th row of pixels Pi+2.

In the array substrate shown in FIG. 1a and FIG. 1b, the pixels electrically connected to the first gate line of all gate line units form a plurality of pixel columns, and the pixel columns electrically connected to the second gate line form a plurality of pixel columns. Multiple columns of pixel columns are alternately arranged. In other embodiments of the present application, the first gate line and the second gate line of two adjacent gate line units may also be electrically connected to a plurality of pixels at different positions, as shown in FIGS. 2a and 2b for details. , wherein, referring to FIG. 2a , which is a schematic diagram of another TFT array substrate capable of realizing dot inversion provided by the embodiment of the present application, the first gate line Gi1 of the i-th gate line unit Gi is electrically connected to A plurality of pixels P100 at the odd positions of the i-th row of pixels Pi, and the second gate line Gi2 of the i-th gate line unit Gi are electrically connected to a plurality of pixels P100 at the even-numbered positions of the i+2 row of pixels Pi+2. pixel; and the first gate line G(i+1)1 of the (i+1)th level gate line unit Gi+1 is electrically connected to a plurality of pixels P100 at even positions of the (i+1)th row of pixels Pi+1 , the second gate line G(i+1)2 of the i+1th gate line unit Gi+1 is electrically connected to a plurality of pixels P200 at odd positions of the i+3th row of pixels Pi+3, i is an odd number; or,

Referring to FIG. 2b , which is a schematic diagram of another TFT array substrate capable of realizing dot inversion provided by the embodiment of the present application, the first gate line Gi1 of the i-th gate line unit Gi is electrically connected to the i-th row For a plurality of pixels P100 at even positions of the pixel Pi, the second gate line Gi2 of the i-th gate line unit Gi is electrically connected to a plurality of pixels at odd positions of the i+2th row of pixels Pi+2; and The first gate line G(i+1)1 of the i+1th level gate line unit Gi+1 is electrically connected to a plurality of pixels P100 at odd positions of the i+1th row of pixels Pi+1, and the ith The second gate line G(i+1)2 of the +1-level gate line unit Gi+1 is electrically connected to a plurality of pixels P200 in the even-numbered positions of the i+3th row of pixels Pi+3, and i is an odd number.

It can be seen from Figures 2a and 2b that, in the TFT array substrate provided by the embodiment of the present application, between multiple pixels driven by the first gate lines of adjacent two-level gate line units, the pixels along the i-th row Alternately arranged in the direction X of Pi; and a plurality of pixels driven by the second gate line of adjacent two-level gate line units are alternately arranged in the direction X parallel to the i-th row of pixels Pi.

In addition, for the TFT array substrate provided in the embodiment of the present application, the second row of pixels P2 to the N+1th row of pixels Pn+1 correspond to the first-level gate line unit G1 to the Nth-level gate line unit Gn between the first gate line and the second gate line; and the first row of pixels P1 is located on the side of the first-level gate line unit G1 away from the second-level gate line unit G2, and the N+2th row of pixels Pn+ 2 is located on the side of the Nth-level gate line unit Gn away from the N-1-th level gate line unit Gn-1.

Corresponding to the TFT array substrate provided in the above embodiment, the embodiment of the present application also provides a driving method for driving the TFT array substrate provided in the above embodiment, wherein the TFT array substrate includes:

A plurality of data lines (D1～Dm) for transmitting data signals;

The first level gate line unit G1 to the Nth level gate line unit Gn are used to transmit gate driving signals, each gate line unit includes a first gate line and a second gate line, and any gate line The first gate line and the second gate line of the line unit simultaneously transmit a gate driving signal;

And, a pixel area including the first row of pixels P1 to the N+2th row of pixels Pn+2;

Wherein, the first gate line of the i-level gate line unit is used to drive a plurality of pixels P100 in the i-th row of pixels, and the second gate line of the i-level gate line unit is used to drive the i+2th row of pixels a plurality of pixels P200, and the plurality of pixels P100 driven by the first gate line of the gate line unit of the i level and the plurality of pixels P200 driven by the second gate line of the gate line unit of the i level are in spatial position Arranged alternately, 1<=i<=N, N is an integer, and the driving methods include:

Carry out step-by-step scanning along the gate line unit G1 of the first level to the gate line unit Gn of the Nth level, and transmit data signals through a plurality of data lines (D1-Dm), wherein, after scanning the gate line unit of the i level , every time two gate line units are scanned, the polarities of the data signals of the multiple data lines (D1˜Dm) are reversed.

Referring to Figure 3a, it is a schematic diagram of pixel polarity distribution when driving a TFT array substrate provided by an embodiment of the present application, wherein i can be defined as 1, and multiple data lines when scanning the first-level gate line unit G1 The polarities of the data signals ( D1 ˜ Dm ) are opposite to those of the multiple data lines ( D1 ˜ Dm ) when scanning the second-level gate line unit G2 and the third-level gate line unit G3 . That is, the data signal polarities of multiple data lines (D1~Dm) when scanning the first-level gate line unit G1 are different from the multiple data signal polarities when scanning the fourth-level gate line unit G4 and the fifth-level gate line unit G5. The data signals of the data lines (D1˜Dm) have the same polarity.

Or, refer to FIG. 3b, which is another schematic diagram of pixel polarity distribution when driving a TFT array substrate provided by the embodiment of the present application, wherein, i can be defined as 2, and the first-level gate line unit G1 and the second-level gate line unit G1 are scanned. The data signal polarity of the multiple data lines (D1～Dm) when the first-level gate line unit G2 is the same as that of the multiple data lines (D1～Dm) when scanning the third-level gate line unit G3 and the fourth-level gate line unit G4. ~Dm) The polarity of the data signal is reversed. That is, the data signal polarity of multiple data lines (D1~Dm) when scanning the first-level gate line unit G1 and the second-level gate line unit G2 is the same as scanning the fifth-level gate line unit G5 and the sixth-level gate line unit G5. The data signal polarities of the plurality of data lines ( D1 to Dm ) in the gate line unit G6 are the same.

The pixel distribution structure in the TFT array substrate shown in Figures 3a and 3b above is consistent with the pixel distribution structure of the TFT array substrate described in Figures 1a and 1b, and is the first gate line and the second gate line of all gate line units. A plurality of pixels driven by the gate lines are arranged correspondingly. When the pixel distribution structure is selected as follows: in all gate line units, the plurality of pixels driven by the first gate lines of two adjacent gate line units are arranged alternately along the direction parallel to the i-th row of pixels Pi ; and between the plurality of pixels driven by the second gate line of the adjacent two-level gate line unit, when the TFT array substrates arranged alternately along the direction parallel to the i-th row of pixels Pi, as shown in FIG. 3c, Another schematic diagram of pixel polarity distribution when driving a TFT array substrate provided in the embodiment of the present application:

Define i as 1, and the data signal polarity of multiple data lines (D1-Dm) when scanning the first-level gate line unit G1 is the same as scanning the second-level gate line unit G2 and the third-level gate line unit In G3, the polarities of the data signals of the plurality of data lines (D1˜Dm) are reversed. That is, the data signal polarities of multiple data lines (D1~Dm) when scanning the first-level gate line unit G1 are different from the multiple data signal polarities when scanning the fourth-level gate line unit G4 and the fifth-level gate line unit G5. The data signals of the data lines (D1˜Dm) have the same polarity.

It can be seen from the above that when the driving method provided by the above-mentioned embodiment is used to drive the TFT array substrate, the pixel units of two adjacent pixels having the same voltage polarity in each column of pixels, and the pixel units in the horizontal direction and vertical direction are realized. The dot inversion method with opposite polarity improves the crosstalk phenomenon and improves the display image effect.

Further, refer to FIG. 4 , which is a schematic diagram of another TFT array substrate capable of realizing point inversion provided by the embodiment of the present application; wherein, the TFT array substrate includes:

A plurality of data lines (D1-Dm) are used to transmit data signals, and the plurality of data lines (D1-Dm) are all electrically connected to the source drive circuit 100, and the data signals are transmitted through the control of the source drive circuit 100;

The first level gate line unit G1 to the Nth level gate line unit Gn are used to transmit gate driving signals, and each gate line unit is electrically connected to the gate driving circuit 200, through the gate driving circuit 200 Controlling the transmission of gate drive signals, each gate line unit includes a first gate line and a second gate line, and the first gate line and the second gate line of any gate line unit transmit the gate drive at the same time signal, that is, the first gate line and the second gate line of any gate line unit are electrically connected, and simultaneously transmit a gate drive signal of the same polarity;

And, a pixel area including the first row of pixels P1 to the N+2th row of pixels Pn+2;

Wherein, the first gate line of the i-level gate line unit is used to drive a plurality of pixels in the i-th row of pixels, and the second gate line of the i-level gate line unit is used to drive the i+2th row of pixels A plurality of pixels, and the plurality of pixels driven by the first gate line of the gate line unit of the i level and the plurality of pixels driven by the second gate line of the gate line unit of the i level are arranged alternately in spatial position, 1 <=i<=N, N is an integer.

The TFT array substrate also includes: a compensation gate line unit, the compensation gate line unit includes a first compensation gate line G1', a second compensation gate line G2', a third compensation gate line G3' and a fourth compensation gate line at least one of the lines G4';

The first compensation gate line G1' is used to drive a plurality of first compensation pixels P300, and the plurality of first compensation pixels P300 are located in the first row of pixels P1, and are connected to the first gate line of the first-level gate line unit G1. A plurality of pixels driven by G11 are arranged alternately; the second compensation gate line G2' is used to drive a plurality of second compensation pixels P400, and the plurality of second compensation pixels P400 are located in the second row of pixels P2, and are connected to the second level gate A plurality of pixels driven by the first gate line G21 of the line unit G2 are arranged alternately;

The third compensation gate line G3' is used to drive a plurality of third pixels P500, and the plurality of third compensation pixels P500 are located in the N+1th row of pixels Pn+1, and are connected to the N-1th level gate line unit Gn- 1 A plurality of pixels driven by the second gate line G(n-1)2 are arranged alternately;

The fourth compensation gate line G4' is used to drive a plurality of fourth compensation pixels P600, and the plurality of fourth compensation pixels P600 are located in the N+2 row of pixels Pn+2, and are connected to the Nth gate line unit Gn. A plurality of pixels driven by the two gate lines Gn2 are alternately arranged.

The compensation gate line unit shown in FIG. 4 of the embodiment of the present application includes first to fourth compensation gate lines. In other embodiments of the present application, the compensation gate line unit may also include a single gate line among the first compensation gate line to the fourth compensation gate line, or include the first compensation gate line to the fourth compensation gate line. A plurality of gate lines among the compensation gate lines is not specifically limited.

Referring to the TFT array substrate provided in the embodiment corresponding to FIG. 4, its driving method is:

Scan along the first compensation gate line G1' to the fourth compensation gate line G4' step by step, and transmit data signals through a plurality of data lines (D1 to Dm), wherein, when scanning the first compensation gate line G1' and When the second compensation gate line G2', the polarity of the data signal of multiple data lines (D1～Dm) is negative; while scanning the first gate line unit G1 and the second gate line unit G2, the multiple data lines The polarity of the data signal of the line (D1～Dm) is positive, and the polarity of the data signal of multiple data lines (D1～Dm) is reversed every time two gate line units are scanned;

And the polarities of the data signals of the multiple data lines (D1-Dm) when scanning the Nth gate line unit and the third compensation gate line G3' are the same as the polarities of the data signals of the multiple data lines (D1-Dm) when scanning the fourth compensation gate line G4' The polarities of the data signals of the data lines (D1-Dm) are opposite, and at this time, the number of N-level gate line units on the TFT array substrate is an odd number;

And if the number of N-level gate line units on the TFT array substrate is an even number, then the poles of the data signals of the multiple data lines when scanning the N-1th level gate line unit and the Nth level gate line unit The polarity is opposite to the polarity of the data signals of the plurality of data lines when scanning the third compensation gate line and the fourth compensation gate line.

For the above-mentioned driving method of the TFT array substrate including the first compensation gate line to the fourth compensation gate line, some steps in the driving method may also be:

When scanning step by step along the first compensation gate line to the fourth compensation gate line, and transmitting data signals through multiple data lines, when scanning the first compensation gate line and the second compensation gate line, multiple data The polarity of the data signal of the multiple data lines is adjusted to be positive; when scanning the first gate line unit and the second gate line unit, the polarity of the data signals of multiple data lines is adjusted to be negative, and each subsequent scan of two levels In the gate line unit, the polarities of the data signals of the plurality of data lines are reversed; or,

The driver method can also be:

When scanning step by step along the first compensation gate line to the fourth compensation gate line and transmitting data signals through multiple data lines, the polarity of the data signals of the multiple data lines when scanning the first compensation gate line In order to adjust to the first polarity; and adjust the polarity of the data signals of the multiple data lines when scanning the second compensation gate line and the first gate line unit G1 to the second polarity opposite to the first polarity , and the polarities of the data signals of multiple data lines are reversed every time two gate line units are scanned;

And when the number of N-level gate line units on the TFT array substrate is an odd number, then the polarity of the data signals of the multiple data lines when scanning the N-1th level gate line unit and the Nth level gate line unit , which is opposite to the polarity of the data signals of the plurality of data lines when scanning the third compensation gate line and the fourth compensation gate line;

And when the number of N-level gate line units on the TFT array substrate is an even number, then the polarity of the data signals of the multiple data lines when scanning the N-level gate line unit and the third compensation gate line is related to the scanning The polarities of the data signals of the plurality of data lines in the fourth compensation gate line are reversed.

It should be noted that, for the TFT array substrate including the compensation gate line unit in this application, it is necessary to select an appropriate driving method according to the number of compensation gate lines in the compensation gate line unit, and finally realize the dot inversion mode.

Secondly, the embodiment of the present application also provides a display panel, including a TFT array substrate, and the TFT array substrate includes: a plurality of data lines for transmitting data signals;

The first level gate line unit to the Nth level gate line unit are used to transmit gate driving signals, each gate line unit includes a first gate line and a second gate line, and any gate line unit The first gate line and the second gate line transmit the gate driving signal at the same time;

And, a pixel area including the first row of pixels to the N+2th row of pixels;

Wherein, the first gate line of the i-level gate line unit is used to drive a plurality of pixels in the i-th row of pixels, and the second gate line of the i-level gate line unit is used to drive the i+2th row of pixels A plurality of pixels, and the plurality of pixels driven by the first gate line of the gate line unit of the i level and the plurality of pixels driven by the second gate line of the gate line unit of the i level are arranged alternately in spatial position, 1 <=i<=N, N is an integer.

Finally, the embodiment of the present application also provides a display device, as shown in FIG. transmit data signals;

The first level gate line unit to the Nth level gate line unit are used to transmit gate driving signals, each gate line unit includes a first gate line and a second gate line, and any gate line unit The first gate line and the second gate line transmit the gate driving signal at the same time;

And, a pixel area including the first row of pixels to the N+2th row of pixels;

Wherein, the first gate line of the i-level gate line unit is used to drive a plurality of pixels in the i-th row of pixels, and the second gate line of the i-level gate line unit is used to drive the i+2th row of pixels A plurality of pixels, and the plurality of pixels driven by the first gate line of the gate line unit of the i level and the plurality of pixels driven by the second gate line of the gate line unit of the i level are arranged alternately in spatial position, 1 <=i<=N, N is an integer.

In the TFT array substrates provided in all the above embodiments of the present application, the arrangement of the gate line units can be arranged arbitrarily, as shown in Figures 5a to 5c, which are the three types of gate line units provided in the embodiments of the present application Arrange the diagram.

Wherein, as shown in FIG. 5a, the gate line units may be arranged in an embedded manner, wherein the first gate line G(i+1)1 of the i+1th level gate line unit Gi+1 is located at the Between the first gate line Gi1 and the second gate line Gi2 of the i-level gate line unit Gi; the second gate line G(i+1)2 of the i+1th level gate line unit Gi+1 is located Between the first gate line G(i+2)1 and the second gate line G(i+2)2 of the (i+2)th gate line unit Gi+2.

As shown in FIG. 5b, the gate line units can be arranged in an externally embedded manner, wherein, the first gate line G(i+1)1 and the second gate line G(i+1)1 of the i+1th level gate line unit Gi+1 The pole line G(i+1)2 is located between the i-th gate line unit Gi and the i+2-th gate line unit Gi+2.

Alternatively, as shown in FIG. 5c, the gate line units can be arranged in a mixed manner, wherein the second gate line Gi2 of the i-th gate line unit Gi is located in the i+1-th gate line unit Gi+1 Between the first gate line G(i+1)1 and the second gate line G(i+1)2, i is an odd number.

In addition, in the TFT array substrates provided in all the above-mentioned embodiments of the present application, in order to reduce the output nodes of the gate drive circuit, in any gate line unit provided in the embodiments of the present application, the first gate line and the second gate The pole lines are electrically connected, and the input end of the first gate line is connected with the input end of the second gate line. Moreover, in order to increase the number of pixels and improve the display effect, in the gate line units of the first level to the gate line units of the Nth level, the signal input ends of the odd-numbered gate line units and the signal input ends of the even-numbered gate line units, They are respectively located on opposite sides of the pixel area (as shown in FIGS. 5 a to 5 c ).

In order to reduce the manufacturing cost and simplify the manufacturing process, when manufacturing the TFT array substrate, the embodiment of the present application can adopt a middle-com structure, that is, refer to FIG. 6, which is a schematic diagram of the TFT array substrate structure provided by the embodiment of the present application. It includes a substrate 61, a first conductive layer 62, a first insulating layer 63, a silicon island layer 64, a second conductive layer 65, a second insulating layer 66, a third conductive layer 67, a third insulating layer 68 and a fourth conductive layer. 69; where,

The first conductive layer 62 includes first-level gate line units to Nth level gate line units and a plurality of gates;

The silicon island layer 64 includes a plurality of silicon islands corresponding to the gates;

The second conductive layer 65 includes the multiple data lines, multiple source/drains corresponding to the silicon islands, multiple gates and multiple source/drains to form TFT transistors;

The third conductive layer 67 includes a common electrode;

The fourth conductive layer 69 includes a plurality of pixel electrodes.

It should be noted that the TFT array substrate provided in the embodiment of the present application can also be fabricated with other structures, and is not limited to the middle-com structure. And, the material of each layer structure is the same as the existing material, and the embodiment of the present application will not describe it in detail.

The TFT array substrate, the driving method, the display panel, and the display device provided in the embodiments of the present application, the TFT array substrate includes: a plurality of data lines for transmitting data signals; the first-level gate line unit to the Nth-level gate line unit , used to transmit the gate drive signal, each gate line unit includes a first gate line and a second gate line, and the first gate line and the second gate line of any gate line unit transmit the gate at the same time a pole driving signal; and, a pixel area including the first row of pixels to the N+2th row of pixels; wherein, the first gate line of the i-th gate line unit is used to drive a plurality of pixels of the i-th row of pixels, The second gate line of the i-level gate line unit is used to drive a plurality of pixels in the i+2 row of pixels, and the plurality of pixels driven by the first gate line of the i-level gate line unit are the same as those of the i-level A plurality of pixels driven by the second gate line of the gate line unit are alternately arranged in spatial positions, 1<=i<=N, where N is an integer.

It can be seen from the above that when scanning step by step along the gate line unit of the first level to the gate line unit of the Nth level, multiple data lines transmit data signals at the same time, wherein, after scanning the gate line unit of the i level, Subsequent scanning of two-level gate line units, the polarity of the data signals of multiple data lines is reversed, and then the pixel units of two adjacent pixels with the same voltage polarity in each column of pixels are compatible with the horizontal direction and vertical direction. The dot inversion method in which the polarity of the pixel units in the direction is opposite improves the crosstalk phenomenon and improves the display image effect.

Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalent technologies, the present invention also intends to include these modifications and variations.

Claims (15)

1. A TFT array substrate, characterized in that, comprising: Multiple data lines for transmitting data signals; The first level gate line unit to the Nth level gate line unit are used to transmit gate driving signals, each gate line unit includes a first gate line and a second gate line, and any gate line unit The first gate line and the second gate line transmit the gate driving signal at the same time; And, a pixel area including the first row of pixels to the N+2th row of pixels; Wherein, the first gate line of the i-level gate line unit is used to drive a plurality of pixels in the i-th row of pixels, and the second gate line of the i-level gate line unit is used to drive the i+2th row A plurality of pixels of the pixel, and the plurality of pixels driven by the first gate line of the i-level gate line unit and the plurality of pixels driven by the second gate line of the i-level gate line unit are spaced The positions are alternately arranged, 1<=i<=N, N is an integer; Wherein, in any gate line unit, the first gate line is electrically connected to the second gate line, and the input end of the first gate line is connected to the input end of the second gate line. 2. The TFT array substrate according to claim 1, wherein the second row of pixels to the N+1th row of pixels are respectively located in the first-level gate line unit to the Nth-level gate Between the first gate line and the second gate line of the pole line unit; And the first row of pixels is located on the side of the first-level gate line unit away from the second-level gate line unit, and the N+2th row of pixels is located on the side of the N-th level gate line unit away from the second-level gate line unit. One side of the N-1th level gate line unit. 3. The TFT array substrate according to claim 1, wherein the first gate line of the i-th gate line unit is electrically connected to a plurality of pixels at odd positions of the i-th row of pixels , the second gate line of the i-th level gate line unit is electrically connected to a plurality of pixels in the even-numbered positions of the i+2th row of pixels; or, The first gate line of the i-level gate line unit is electrically connected to a plurality of pixels in the even-numbered position of the i-th row of pixels, and the second gate line of the i-level gate line unit is electrically are connected to multiple pixels at odd positions of the i+2th row of pixels. 4. The TFT array substrate according to claim 1, wherein the first gate line of the i-th gate line unit is electrically connected to a plurality of pixels at odd positions of the i-th row of pixels , the second gate line of the i-th level gate line unit is electrically connected to a plurality of pixels in the even-numbered positions of the i+2th row of pixels; and the i+1th level gate line unit The first gate line is electrically connected to a plurality of pixels in the even-numbered positions of the i+1th row of pixels, and the second gate line of the i+1th gate line unit is electrically connected to the first gate line unit. A plurality of pixels in i+3 rows of pixels at odd positions, where i is an odd number; or, The first gate line of the i-level gate line unit is electrically connected to a plurality of pixels in the even-numbered position of the i-th row of pixels, and the second gate line of the i-level gate line unit is electrically A plurality of pixels at odd positions are electrically connected to the i+2th row of pixels; and the first gate line of the i+1th gate line unit is electrically connected to the i+1th row of pixels For a plurality of pixels at odd positions, the second gate line of the i+1th level gate line unit is electrically connected to a plurality of pixels at even positions of the i+3th row of pixels, i is an odd number . 5. The TFT array substrate according to claim 1, further comprising a compensation gate line unit, the compensation gate line unit comprising a first compensation gate line, a second compensation gate line, a third compensation gate line at least one of the gate line and the fourth compensated gate line; The first compensation gate line is used to drive a plurality of first compensation pixels, and the plurality of first compensation pixels are located in the first row of pixels, and are connected to the first gate of the first-level gate line unit. A plurality of pixels driven by polar lines are arranged alternately; The second compensation gate line is used to drive a plurality of second compensation pixels, and the plurality of second compensation pixels are located in the second row of pixels, and are connected to the first gate of the second-level gate line unit. A plurality of pixels driven by polar lines are arranged alternately; The third compensation gate line is used to drive a plurality of third compensation pixels, and the plurality of third compensation pixels are located in the N+1th row of pixels, and are united with the N-1th level gate line A plurality of pixels driven by the second gate line are arranged alternately; The fourth compensation gate line is used to drive a plurality of fourth compensation pixels, and the plurality of fourth compensation pixels are located in the N+2th row of pixels, and are connected to the Nth level gate line unit. A plurality of pixels driven by two gate lines are alternately arranged. 6. The TFT array substrate according to claim 1, wherein the first gate line of the i+1th level gate line unit is located at the first gate line of the ith level gate line unit and between the second gate line; The second gate line of the (i+1)th gate line unit is located between the first gate line and the second gate line of the (i+2)th gate line unit. 7. The TFT array substrate according to claim 1, wherein the first gate line and the second gate line of the (i+1)th level gate line unit are located in the i-th level gate line unit and between the (i+2)th level gate line unit. 8. The TFT array substrate according to claim 1, wherein the second gate line of the i-th gate line unit is located at the first gate line of the i+1-th gate line unit and the second gate line, i is an odd number. 9. The TFT array substrate according to claim 1, wherein in the first-level gate line units to the Nth level gate line units, the signal input ends of the odd-numbered gate line units are connected to the even-numbered gate lines. The signal input ends of the line units are respectively located on opposite sides of the pixel area. 10. The TFT array substrate according to claim 1, characterized in that it comprises a substrate, a first conductive layer, a first insulating layer, a silicon island layer, a second conductive layer, a second insulating layer, a third conductive layer, The third insulating layer and the fourth conductive layer; wherein, The first conductive layer includes the first-level gate line unit to the Nth level gate line unit and a plurality of gates; The silicon island layer includes a plurality of silicon islands corresponding to the gate; The second conductive layer includes the multiple data lines, multiple source/drain electrodes corresponding to silicon islands, the multiple gate electrodes and multiple source/drain electrodes form TFT transistors; The third conductive layer includes a common electrode; The fourth conductive layer includes a plurality of pixel electrodes. 11. A driving method for driving a TFT array substrate, wherein the TFT array substrate comprises: a plurality of data lines for transmitting data signals; The first level gate line unit to the Nth level gate line unit are used to transmit gate driving signals, each gate line unit includes a first gate line and a second gate line, and any gate line unit The first gate line and the second gate line transmit the gate driving signal at the same time; And, a pixel area including the first row of pixels to the N+2th row of pixels; Wherein, the first gate line of the i-level gate line unit is used to drive a plurality of pixels in the i-th row of pixels, and the second gate line of the i-level gate line unit is used to drive the i+2th row A plurality of pixels of the pixel, and the plurality of pixels driven by the first gate line of the i-level gate line unit and the plurality of pixels driven by the second gate line of the i-level gate line unit are spaced The positions are alternately arranged, 1<=i<=N, N is an integer; Wherein, in any gate line unit, the first gate line is electrically connected to the second gate line, and the input end of the first gate line is connected to the input end of the second gate line; The driving method includes: Carry out step-by-step scanning along the first-level gate line unit to the N-th level gate line unit, and transmit data signals through the plurality of data lines, wherein, after scanning the i-th level gate line unit, every scan In the two-stage gate line unit, the polarities of the data signals of the plurality of data lines are reversed. 12. The driving method according to claim 11, wherein the i is 1, and the polarity of the data signals of the plurality of data lines when scanning the first-level gate line unit is different from that of scanning the The data signal polarities of the plurality of data lines in the second-level gate line unit and the third-level gate line unit are opposite. 13. The driving method according to claim 11, wherein the i is 2, and the plurality of data lines when scanning the first-level gate line unit and the second-level gate line unit The polarity of the data signal is opposite to the polarity of the data signals of the plurality of data lines when scanning the third-level gate line unit and the fourth-level gate line unit. 14. A display panel, characterized in that it includes a TFT array substrate, and the TFT array substrate includes: a plurality of data lines for transmitting data signals; The first level gate line unit to the Nth level gate line unit are used to transmit gate driving signals, each gate line unit includes a first gate line and a second gate line, and any gate line unit The first gate line and the second gate line transmit the gate driving signal at the same time; And, a pixel area including the first row of pixels to the N+2th row of pixels; Wherein, the first gate line of the i-level gate line unit is used to drive a plurality of pixels in the i-th row of pixels, and the second gate line of the i-level gate line unit is used to drive the i+2th row A plurality of pixels of the pixel, and the plurality of pixels driven by the first gate line of the i-level gate line unit and the plurality of pixels driven by the second gate line of the i-level gate line unit are spaced The positions are alternately arranged, 1<=i<=N, N is an integer; Wherein, in any gate line unit, the first gate line is electrically connected to the second gate line, and the input end of the first gate line is connected to the input end of the second gate line. 15. A display device, characterized in that it includes a display panel, the display panel includes a TFT array substrate, and the TFT array substrate includes: a plurality of data lines for transmitting data signals; The first level gate line unit to the Nth level gate line unit are used to transmit gate driving signals, each gate line unit includes a first gate line and a second gate line, and any gate line unit The first gate line and the second gate line transmit the gate driving signal at the same time; And, a pixel area including the first row of pixels to the N+2th row of pixels; Wherein, the first gate line of the i-level gate line unit is used to drive a plurality of pixels in the i-th row of pixels, and the second gate line of the i-level gate line unit is used to drive the i+2th row A plurality of pixels of the pixel, and the plurality of pixels driven by the first gate line of the i-level gate line unit and the plurality of pixels driven by the second gate line of the i-level gate line unit are spaced The positions are alternately arranged, 1<=i<=N, N is an integer; Wherein, in any gate line unit, the first gate line is electrically connected to the second gate line, and the input end of the first gate line is connected to the input end of the second gate line.