CN103268047B - A kind of LTPS array base palte and manufacture method thereof - Google Patents

Abstract

The invention discloses an LTPS array substrate and a manufacturing method thereof. The LTPS array substrate includes: a substrate; a patterned light-shielding layer formed on the substrate; wherein it also includes a patterned storage layer, a buffer layer formed on the substrate and the patterned light-shielding layer A patterned polysilicon layer formed on the buffer layer; a gate insulating layer formed on the patterned polysilicon layer and the buffer layer; a gate electrode line and a common electrode formed on the gate insulating layer line; the patterned storage layer and the light-shielding layer are located on the same layer, the patterned storage layer, the patterned polysilicon layer corresponding to the patterned storage layer, and the buffer layer sandwiched therebetween constitute a storage capacitor. By adopting the LTPS array substrate of the present invention, the storage capacitance of pixels can be increased without changing the aperture ratio.

Description

A kind of LTPS array substrate and its manufacturing method

technical field

The invention relates to flat panel display technology, in particular to an LTPS array substrate and a manufacturing method thereof.

Background technique

Low temperature polysilicon (LTPS) thin film transistor liquid crystal display is different from the traditional amorphous silicon thin film transistor liquid crystal display, its electron mobility can reach more than 200cm2/V-sec, which can effectively reduce the area of thin film transistor devices , so as to increase the aperture ratio, and reduce the overall power consumption while improving the brightness of the display. In addition, the higher electron mobility can integrate part of the driving circuit on the glass substrate, reducing the number of driving ICs, and can also greatly improve the reliability of the liquid crystal display panel, thereby greatly reducing the manufacturing cost of the panel. Therefore, the LTPS thin film transistor liquid crystal display has gradually become a research hotspot. The LTPS thin film transistor liquid crystal display mainly includes an array substrate and a color filter substrate arranged opposite to it.

As shown in FIG. 1 , the LTPS array substrate 100 in the prior art mainly includes: a substrate 101, a light-shielding layer 102, a buffer layer 103, a polysilicon layer 104, a gate insulating layer 105, a gate 106, a source electrode/drain 107 and a common electrode 108. Wherein, the polysilicon layer 104, gate insulating layer 105, gate 106 and source/drain 107 constitute a thin film transistor, and the light shielding layer 102 is formed on the substrate 101 corresponding to the channel position of the thin film transistor , used to prevent the influence of the backlight on the channel. Wherein, the common electrode 108 corresponds to the polysilicon layer 104 , and the capacitor C _CP formed by the common electrode 108 separated by the gate insulating layer 105 and the polysilicon layer 104 serves as a storage capacitor of the corresponding pixel. In order to increase the storage capacitance, it is usually chosen to increase the area of the common electrode 108 . However, after the common electrodes 108 are increased, the aperture ratio of the array substrate 100 will decrease.

In addition, because the position of the light-shielding layer 102 is opposite to that of the polysilicon layer 104 and is separated by the buffer layer 103, the light-shielding layer 102, the polysilicon layer 104 and the buffer layer 103 will form a parasitic capacitance C _LP , the parasitic capacitance C _LP Existence will result in an increase in leakage current.

It can be seen that there is a contradiction between increasing the storage capacitance and increasing the aperture ratio in the prior art, and the leakage current is also increased due to the existence of the parasitic capacitance C _LP , which will affect the development of the LTPS array substrate.

Contents of the invention

The invention provides an LTPS array substrate and a manufacturing method thereof, which solves the contradiction between increasing the storage capacitance and increasing the aperture ratio, so as to achieve the purpose of increasing the storage capacitance without affecting the aperture ratio.

On the other hand, the present invention can also solve the problem that the leakage current increases due to the parasitic capacitance C _LP , and reduce the parasitic capacitance C _LP , so as to achieve the purpose of reducing the leakage current.

In order to solve the above technical problems, the present invention provides an LTPS array substrate, comprising:

a substrate;

a patterned light-shielding layer formed on the substrate;

a buffer layer formed on the substrate and the patterned light-shielding layer;

a patterned polysilicon layer formed on the buffer layer;

a gate insulating layer formed on the patterned polysilicon layer and the buffer layer;

gate electrode lines and common electrode lines formed on the gate insulating layer;

Wherein, it also includes a patterned storage layer, the patterned storage layer is located on the same layer as the light-shielding layer, the patterned storage layer, the patterned polysilicon layer corresponding to the patterned storage layer layers and the buffer layer sandwiched between them form a storage capacitor.

Optionally, in the LTPS array substrate, the thickness of the buffer layer between the patterned light-shielding layer and the patterned polysilicon layer is greater than that of the patterned storage layer and the patterned polysilicon layer The thickness of the buffer layer in between.

Optionally, in the LTPS array substrate, the common electrode lines, the patterned polysilicon layer corresponding to the common electrode lines, and the gate insulating layer sandwiched therebetween form another storage capacitor.

Optionally, the LTPS array substrate further includes a through hole penetrating through the gate insulating layer and the buffer layer, and the common electrode line is connected to the patterned storage layer through the through hole.

Correspondingly, the present invention also provides a method for manufacturing an LTPS array substrate, including:

providing a substrate;

forming a light-shielding layer on the substrate;

Etching the light-shielding layer to form a patterned light-shielding layer and a patterned storage layer;

forming a buffer layer on the patterned light-shielding layer, the patterned storage layer and the substrate;

forming a patterned polysilicon layer on the buffer layer;

forming a gate insulating layer on the patterned polysilicon layer and the buffer layer;

forming gate electrode lines and common electrode lines on the gate insulating layer;

Wherein, the patterned storage layer, the patterned polysilicon layer corresponding to the patterned storage layer, and the buffer layer interposed therebetween form a storage capacitor.

Optionally, in the manufacturing method of the LTPS array substrate, after the step of forming the buffer layer on the patterned light-shielding layer, the patterned storage layer and the substrate, further include: The thickness of the buffer layer corresponding to the location of the storage layer.

Optionally, in the manufacturing method of the LTPS array substrate, after the step of forming a gate insulating layer on the patterned polysilicon layer and the buffer layer, further comprising: forming a gate insulating layer in the gate insulating layer and the buffer layer A through hole, through which the common electrode line is connected to the patterned storage layer.

On the LTPS array substrate provided by the present invention, a patterned storage layer is included, the patterned storage layer is located on the same layer as the light-shielding layer, and the patterned storage layer and the patterned storage layer are The corresponding patterned polysilicon layer and the interposed buffer layer form a storage capacitor. It can be seen that, in addition to another storage capacitor formed by the patterned polysilicon layer corresponding to the common electrode line, the storage capacitor of the pixel of the LTPS array substrate also includes a storage capacitor formed by the patterned storage layer and the patterned polysilicon layer. capacitance. Therefore, on the premise that the area of the common electrode layer does not change, the storage capacitor of the pixel additionally increases the storage capacitor formed by the storage capacitor including the patterned storage layer and the patterned polysilicon layer. That is to say, under the premise that the aperture ratio does not change, the storage capacitance of the pixel increases.

In addition, the thickness of the buffer layer between the light shielding layer and the patterned polysilicon layer is greater than the thickness of the buffer layer between the patterned storage layer and the patterned polysilicon layer. The parasitic capacitance C _LP formed by the light-shielding layer, the patterning and the buffer layer, because the thickness of the dielectric layer and the buffer layer between them is small, the parasitic capacitance C _LP is also correspondingly reduced, thereby reducing the leakage current .

Description of drawings

FIG. 1 is a schematic structural view of an LTPS array substrate in the prior art;

2 is a schematic structural diagram of a pixel on an LTPS array substrate according to Embodiment 1 of the present invention;

3 to 14 are schematic diagrams of each step of the manufacturing method of the LTPS array substrate in Embodiment 1 of the present invention;

15 is a schematic structural diagram of an LTPS array substrate according to Embodiment 2 of the present invention;

FIG. 16 is a schematic structural diagram of an LTPS array substrate according to Embodiment 3 of the present invention.

Detailed ways

In order to make the purpose, technical solution and advantages of the present invention more clear, the following will be further described in detail in conjunction with the accompanying drawings.

Embodiment one

The manufacturing method of the LTPS (low temperature poly-silicon, LTPS for short) array substrate of this embodiment will be described in detail below with reference to FIG. 2 to FIG. 14 .

FIG. 2 is a structural diagram of a pixel on the LTPS array substrate of this embodiment. The detailed manufacturing process is described below with the sections along the II' line and II-II' line in FIG. 2:

Step 1, as shown in FIG. 3 , a substrate 201 is provided, and the substrate 201 is usually a transparent glass substrate;

Step 2, as shown in FIG. 4 , forming a light-shielding layer 202 on the substrate 201, exposing the light-shielding layer 202, and then etching the light-shielding layer 202 to form a patterned light-shielding layer 202A and a patterned storage layer 202B, the material of the light-shielding layer 202 is, for example, molybdenum-aluminum alloy, chromium metal, molybdenum metal, or other materials having both light-shielding function and conductive property;

Step 3, as shown in FIG. 5, a buffer layer 203 is formed on the substrate 201 to cover the patterned light-shielding layer 202A and the patterned storage layer 202B. In order to prevent harmful substances in the substrate 201, such as alkali metal The impact of ions on the performance of the polysilicon layer, pre-cleaning is performed before depositing the buffer layer 203, and then the buffer layer 203 is deposited on the substrate 201 by PECVD;

Step 4, as shown in FIG. 6, a layer of amorphous silicon is deposited on the buffer layer 203 by PECVD, and a high-temperature oven is used to perform a dehydrogenation process on the amorphous silicon layer to prevent the crystallization process from occurring. The hydrogen explosion phenomenon and the effect of reducing the defect state density inside the film after crystallization. After the dehydrogenation process is completed, the LTPS process is carried out, and the amorphous silicon layer is crystallized by crystallization methods such as laser annealing (ELA), metal-induced crystallization (MIC), and solid-phase crystallization (SPC). A polysilicon layer is formed on the buffer layer 203 . Next, on the polysilicon layer, different ion implantation regions are formed by means of exposure, and ion implantation is performed on the polysilicon layer to form channel regions and source and drain regions respectively. Next, photolithography is performed on the polysilicon layer, and a patterned polysilicon layer 204 is formed on the buffer layer 203. Part of the patterned polysilicon layer 204 is connected with the patterned light shielding layer 202A and the patterned storage layer. 202B overlapping;

Step 5, as shown in FIG. 7 , a gate insulating layer 205 is formed on the patterned polysilicon layer 204 and buffer layer 203 by PECVD, and the material of the gate insulating layer 205 is, for example, nitrogen silicide, oxysilicide Dielectric materials such as objects;

Step 6, as shown in FIG. 8 , a gate metal layer is formed on the gate insulating layer 205 by using a sputtering process, and then a gate electrode line 2051 is formed on the gate insulating layer 205 through a photolithography process. and the common electrode line 2052, wherein the common electrode line 2052 overlaps with the patterned storage layer 202B, and the material of the gate metal layer is, for example, molybdenum aluminum alloy, chromium metal, molybdenum metal or other low-resistance conductive materials ;

Step 6, as shown in FIG. 9, a dielectric layer 206 is formed on the gate metal layer by using PECVD. Forming first through holes 2061 and 2062 through the dielectric layer 206 and the gate insulating layer 205 by etching, and the first through holes 2061 and 2062 expose part of the patterned polysilicon layer 204;

Step 7, as shown in FIG. 10 , a data metal layer is formed on the substrate 201 by sputtering, and then a data line is formed through a photolithography process, and source electrodes are formed in the first through holes 2061 and 2062 and the drain electrode 207, the material of the data metal layer is, for example, molybdenum aluminum alloy, chromium metal, molybdenum metal or other low-resistance conductive materials;

Step eight, as shown in FIG. 11 , form a flat layer 208 and a first transparent electrode layer 209 on the substrate 201 after step seven. The material of the flat layer 208 is, for example, an organic film; The second through hole 2081, the position of the second through hole 2081 corresponds to the position of the drain, the second through hole 2081 penetrates through the planar layer 208 and the first transparent electrode layer 209 and exposes the drain ; Preferably, the area of the second through hole 2081 is greater than or equal to the area of the first through hole 2062 corresponding to the drain;

Step 9, as shown in FIG. 12 , form a third through hole 2091 in the first transparent electrode layer 209, the position of the third through hole 2091 corresponds to the position of the second through hole 2081, and a part of the flat surface is exposed. Layer 208;

Step ten, as shown in FIG. 13 , a protective layer 210 is formed on the first transparent electrode layer 209 and in the second through hole 2081 and the third through hole 2091 by PECVD, and the material of the protective layer 210 is silicon nitride ; Next, forming a fourth through hole 2101 through the protective layer 210 and the planar layer 208 by dry etching, and the fourth through hole 2101 exposes the drain;

Step eleven, as shown in FIG. 14 , a second transparent electrode layer 211 is formed on the protective layer 210 and in the fourth through hole 2101 by sputtering, and the second transparent electrode layer 211 passes through the fourth through hole 2101 connected with the drain to form a pixel electrode.

So far, an LTPS array substrate 200 as shown in FIG. The buffer layer 203 on the substrate 201 and the patterned light-shielding layer 202A; the patterned polysilicon layer 204 formed on the buffer layer 203; the gate formed on the patterned polysilicon layer 204 and the buffer layer 203 The insulating layer 205 ; the gate electrode line 2051 and the common electrode line 2052 formed on the gate insulating layer 205 . Wherein, the patterned storage layer 202B is located on the same layer as the patterned light-shielding layer 202A, the patterned storage layer 202B, the patterned polysilicon layer 204 corresponding to the patterned storage layer 202B and the buffer layer 203 sandwiched therebetween form a storage capacitor C _bp1 .

In addition, the common electrode line 2052 , the patterned polysilicon layer 204 corresponding to the common electrode line 2052 and the gate insulating layer 205 sandwiched therebetween form another storage capacitor C _cp . In this embodiment, another storage capacitor C _cp is connected in parallel with the storage capacitor C _bp1 to jointly form the storage capacitor C _s of the pixel. Therefore, without changing the common electrode line 2052 of the storage capacitor C _s , a parallel storage capacitor C _bp1 is added, that is, without changing the aperture ratio, the storage capacitor C _s is increased.

Embodiment two

The difference between this embodiment and Embodiment 1 is that after Step 3 and before Step 4 of the embodiment, the following step is also included: use dry etching to thin the buffer corresponding to the position of the patterned storage layer 202B The thickness of layer 203 .

Except for the above steps, the other steps of this embodiment are exactly the same as those of the first embodiment, for details, please refer to the first embodiment.

As shown in FIG. 15 , in the LTPS array substrate 200 provided in this embodiment, after the buffer layer 203 is thinned, the buffer between the patterned light-shielding layer 202A and the patterned polysilicon layer 204 The thickness t1 of the layer 203 is greater than the thickness t2 of the buffer layer 203 between the patterned storage layer 202B and the patterned polysilicon layer 204 . Preferably, the thickness t1 of the buffer layer between the patterned light-shielding layer 202A and the patterned polysilicon layer 204 is The thickness t2 of the buffer layer between the patterned storage layer 202B and the patterned polysilicon layer 204 is

In the manufacturing process of the LTPS array substrate 200 of this embodiment, because the thinning step of the buffer layer is added, the buffer layer between the patterned storage layer 202B and the patterned polysilicon layer 204 can be thinned. The reduced thickness of 203 increases the storage capacitor C _bp1 , thereby further increasing the overall storage capacitor Cs of the pixel.

On the other hand, because of the increased thinning step of the buffer layer, the thickness of the buffer layer 203 between the patterned light-shielding layer 202A and the patterned polysilicon layer 204 can be made relatively thick, so that the The patterned light-shielding layer 202A, the patterned polysilicon layer 204 corresponding to the patterned light-shielding layer 202A, and the buffer layer 203 therebetween form a reduced parasitic capacitance _Cbp2 , and the reduction of the parasitic capacitance _Cbp2 can effectively reduce the leakage current .

Embodiment three

The difference between this embodiment and Embodiment 1 or Embodiment 2 is that after Step 5 and before Step 6, the following step is further included: forming a third via hole penetrating through the gate insulating layer 205 and the buffer layer 203 2054, the third through hole 2054 exposes part of the patterned storage layer 202B. After step six, the common electrode line 2052 is connected to the patterned storage layer 202B through the third via hole 2054 .

In this embodiment, except for the above steps, other steps are exactly the same as those in Embodiment 1 or Embodiment 2. For details, please refer to Embodiment 1 or Embodiment 2.

As shown in FIG. 16, in the LTPS array substrate 200 provided in this embodiment, the common electrode line 2052 is connected to the patterned storage layer 202B through the third through hole 2054, so that the storage capacitor C _bp1 The potential can be consistent with the potential of the storage capacitor C _cp , so that the charging and discharging of the storage capacitor C _bp1 becomes controllable, ensuring that the pixel storage capacitor C _s is more controllable and more efficient under the premise of increasing the pixel storage capacitor C _s Stablize.

To sum up, in addition to another storage capacitor formed by the patterned polysilicon layer corresponding to the common electrode line, the storage capacitor of the pixel of the LTPS array substrate provided by the present invention also includes the patterned storage layer and A storage capacitor formed by a patterned polysilicon layer. Therefore, on the premise that the area of the common electrode layer does not change, the storage capacity of the pixel is increased by the storage capacity formed by the storage capacity including the patterned storage layer and the patterned polysilicon layer. That is to say, under the premise that the aperture ratio does not change, the storage capacitance of the pixel increases.

Obviously, those skilled in the art can make various changes and modifications to the invention without departing from the spirit and scope of the invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and equivalent technologies thereof, the present invention also intends to include these modifications and variations.

Claims (7)

1. A LTPS array substrate, comprising: a substrate; a patterned light-shielding layer formed on the substrate; a buffer layer formed on the substrate and the patterned light-shielding layer; a patterned polysilicon layer formed on the buffer layer; a gate insulating layer formed on the patterned polysilicon layer and the buffer layer; gate electrode lines and common electrode lines formed on the gate insulating layer; It is characterized in that it also includes a patterned storage layer, the patterned storage layer is located on the same layer as the light-shielding layer, the patterned storage layer and the patterned storage layer corresponding to the patterned storage layer The polysilicon layer and the buffer layer sandwiched therebetween form a storage capacitor. 2. The LTPS array substrate according to claim 1, wherein the thickness of the buffer layer between the patterned light-shielding layer and the patterned polysilicon layer is greater than that between the patterned storage layer and the patterned The thickness of the buffer layer between the patterned polysilicon layers. 3. The LTPS array substrate according to claim 1, wherein the common electrode line, the patterned polysilicon layer corresponding to the common electrode line, and the gate insulating layer interposed therebetween form another memory capacitance. 4. The LTPS array substrate according to claim 1 or 2, further comprising a through hole penetrating through the gate insulating layer and the buffer layer, the common electrode line passes through the through hole and the patterned storage layer connection. 5. A method for manufacturing an LTPS array substrate, comprising: providing a substrate; forming a light-shielding layer on the substrate; Etching the light-shielding layer to form a patterned light-shielding layer and a patterned storage layer; forming a buffer layer on the patterned light-shielding layer, the patterned storage layer and the substrate; forming a patterned polysilicon layer on the buffer layer; forming a gate insulating layer on the patterned polysilicon layer and the buffer layer; forming gate electrode lines and common electrode lines on the gate insulating layer; Wherein, the patterned storage layer, the patterned polysilicon layer corresponding to the patterned storage layer, and the buffer layer interposed therebetween form a storage capacitor. 6. The method for manufacturing an LTPS array substrate according to claim 5, further comprising: thinning and The thickness of the buffer layer corresponding to the position of the patterned storage layer. 7. The method for manufacturing an LTPS array substrate as claimed in claim 5 or 6, further comprising: after the step of forming a gate insulating layer on the patterned polysilicon layer and the buffer layer: Through holes are formed in the insulating layer and the buffer layer, and the common electrode lines are connected to the patterned storage layer through the through holes.