CN102735263A - Whole-course real-time detection system of spatial stereoscopic plotting camera time synchronization accuracy and method thereof - Google Patents

Abstract

Disclosed are a whole-course real-time detection system of spatial stereoscopic plotting camera time synchronization accuracy and a method thereof. The invention relates to a spatial stereoscopic plotting camera and solves the problem that dynamic change of camera time synchronization errors during the spatial stereoscopic plotting camera operation process can not be detected at real time for a long time by the use of a present common device. The system comprises: a second pulse and line/frame synchronising signal input cable, a second pulse and line/frame synchronising signal transfer unit, a second pulse and line/frame synchronising signal output cable, a FPGA time setting unit, a data collection card, a bus watching cable, a bus communication card and a data handling machine system. According to the method, image time setting information is directly received from internal bus through a bus watching mode, thus substantially reducing the time of separating image data and extracting image time setting information. By the adoption of the system, real-time measurement, recording and display of spatial stereoscopic plotting camera time synchronization accuracy are realized. According to the invention, real-time detection and whole-course recording of dynamic changes of camera time synchronization errors can be realized during the photographing process of the spatial stereoscopic plotting camera.

Description

System and method for whole-process real-time detection of time synchronization accuracy of spatial stereoscopic mapping cameras

technical field

The invention relates to a spatial three-dimensional surveying and mapping camera, in particular to a system and method for whole-process real-time detection of the time synchronization accuracy of a spatial three-dimensional surveying and mapping camera.

Background technique

The space stereo mapping camera uses the satellite as a platform to measure the digital map, digital elevation map and digital orthophoto map of the surface of the earth and other planets through the acquired stereo image, attitude, orbital position and other information. Planning, resource census and other fields play an important role. Since the position and attitude of the satellite are constantly changing during flight, if the camera’s time synchronization accuracy is not high, even if the orbit positioning accuracy and attitude measurement accuracy are high, the spatial stereoscopic mapping camera’s mapping accuracy will be reduced due to the mismatch between the image and position, attitude, etc. Therefore, the camera time synchronization accuracy is an important factor affecting the mapping accuracy of the spatial stereo mapping camera.

The spatial three-dimensional mapping camera receives the GPS second pulse and time stamp information sent by the GPS receiver to establish a camera time system, and regularly collects image time synchronization information during the photography process. The image time synchronization information consists of the line/frame number of a certain line/frame image, the Composed of seconds and microseconds at the start time of line/frame image exposure. The camera time synchronization error is the difference between the time of a line/frame image recorded in the image time synchronization information and the real time of the exposure start moment (based on the time synchronization source, that is, the GPS receiver time system). When the imaging unit of the spatial stereoscopic mapping camera adopts a linear array CCD, it returns a line synchronization signal, and when an area array CCD is used, it returns a frame synchronization signal, and the edge of the line synchronization signal or frame synchronization signal represents the exposure start moment.

In addition to establishing a high-precision time system, the camera controller of the space stereoscopic mapping camera must complete multiple tasks such as complex image movement speed calculation, communication with the star host, control of the imaging unit and focus adjustment, so the central processing unit is generally used (CPU) or digital signal processor (DSP) as the core processing element. Since the camera controller uses software to achieve time synchronization, and has to complete multiple complex tasks, various errors will be introduced in the process of time synchronization, timekeeping and time use. The time synchronization error of the spatial stereoscopic mapping camera is a variety of errors combined results. This causes the time synchronization error to change with the change of the working sequence of the camera controller. During the ground test, the real-time detection of the dynamic change of the time synchronization error during the working process of the spatial three-dimensional mapping camera is the premise to ensure the time synchronization accuracy of the spatial three-dimensional mapping camera. and foundation.

Since the spatial stereoscopic mapping camera can continuously take pictures for dozens of minutes or even several hours during work, conventional instruments such as oscilloscopes and logic analyzers cannot perform long-term detection with high sampling frequency due to the limitation of storage depth. Moreover, since the camera time synchronization accuracy is finally reflected in the image time synchronization information inserted into the image auxiliary data, it is difficult to realize the real-time detection of the time synchronization accuracy in the normal working process of the camera through conventional instruments.

Contents of the invention

In order to solve the problem that the existing conventional instruments cannot detect the dynamic change of the camera time synchronization error during the working process of the spatial three-dimensional surveying and mapping camera in real time for a long period of time, the present invention provides a whole-process real-time detection system and method for the time synchronization accuracy of the spatial three-dimensional surveying and mapping camera.

The whole process real-time detection system for the time synchronization accuracy of spatial stereoscopic mapping camera, the system includes the second pulse and line/frame synchronization signal input cable, the second pulse and line/frame synchronization signal conversion unit, the second pulse and line/frame synchronization signal output cable, FPGA time synchronization unit, data acquisition card, bus monitoring cable, bus communication card and data processing computer system;

The second pulse and line/frame synchronization signal input cable is connected with the second pulse and line/frame synchronization signal conversion unit, and the second pulse and line/frame synchronization signal conversion unit receives the second pulse and line/frame synchronization signal input cable The input GPS second pulse signal and line/frame synchronization signal, and divide the GPS second pulse signal and line/frame synchronization signal into two channels, one GPS second pulse signal and line/frame synchronization signal are sent to the FPGA time synchronization unit, and the other The GPS second pulse signal and line/frame synchronization signal are sent to the second pulse and line/frame synchronization signal output cable; the second pulse and line/frame synchronization signal output cable transmits the GPS second pulse signal and line/frame synchronization signal to the spatial stereo Mapping camera controller;

The FPGA time synchronization unit is connected with the data acquisition card, and the FPGA time synchronization unit is composed of a level conversion chip, an FPGA and a high stability crystal oscillator, and the level conversion chip converts the GPS second pulse signal and the line/frame synchronization signal into a TTL level Signal; the FPGA receives the TTL level signal and the clock signal produced by the high-stability crystal oscillator; the FPGA generates FPGA time synchronization data according to the GPS second pulse signal, row/frame synchronization signal and clock signal, and each row generates a group of FPGA time synchronization data and data sending trigger signal, the FPGA time synchronization unit sends the FPGA time synchronization data and data sending trigger signal to the data acquisition card;

Said data acquisition card receives FPGA time synchronization data and data sending trigger signal sent by FPGA time synchronization unit, and sends to data processing computer system;

The bus monitoring cable is connected to the communication bus between the spatial stereoscopic surveying and mapping camera imaging unit and the spatial stereoscopic surveying and mapping camera controller, and the bus monitoring cable receives the image timing information sent by the spatial stereoscopic surveying and mapping camera controller to the spatial stereoscopic surveying and mapping camera imaging unit , and sent to the bus communication card;

The bus communication card receives the image timing information transmitted by the bus monitoring cable, and transmits the received image timing information to the data processing computer system;

The data processing computer system is connected with the data acquisition card and the bus communication card. The data processing computer system is composed of a data processing computer, data receiving and storage software and data processing software. The data processing computer and the data receiving and storage software receive the data acquisition card to transmit The FPGA time synchronization data and the image time synchronization information transmitted by the bus communication card are stored on the hard disk in the form of files; the data processing software reads the image time synchronization information and FPGA time synchronization data from the hard disk, and calculates the corresponding Camera time synchronization error, and the obtained results are recorded in the hard disk, and displayed in real time in the form of curves.

The whole-process real-time detection method for the time synchronization accuracy of a spatial stereo surveying and mapping camera comprises the following steps:

Step A, disconnect the GPS second pulse connection cable between the GPS receiver or GPS simulation device and the spatial stereoscopic mapping camera controller, and disconnect the line/frame synchronization signal between the spatial stereoscopic mapping imaging unit and the spatial stereoscopic mapping camera controller The cable; connect the input end of the second pulse and line/frame synchronization signal input cable to the GPS second pulse output interface of the GPS receiver or GPS simulation equipment and the line/frame synchronization signal output interface of the spatial stereo mapping imaging unit; the second pulse The output end of the line/frame synchronization signal input cable is connected to the second pulse and line/frame synchronization signal conversion unit; the input end of the second pulse and line/frame synchronization signal output cable is connected to the second pulse and line/frame synchronization signal conversion unit. Connect the unit, connect the output end of the second pulse and line/frame synchronization signal output cable to the second pulse and line/frame synchronization signal input interface of the spatial stereoscopic mapping camera controller, and enter step B;

Step B, reset the FPGA time synchronization unit, set the time scale value sent by the GPS receiver or GPS simulation device to the spatial three-dimensional mapping camera controller and the number of second pulses sent to the second pulse and line/frame synchronization signal conversion unit One-to-one correspondence, then the GPS receiver or GPS simulation device starts to send the GPS second pulse and time scale value, and enters step C;

Step C, the second pulse and line/frame synchronization signal conversion unit divides the GPS second pulse signal and the line/frame synchronization signal into two paths, and sends one of the GPS second pulse signal and the line/frame synchronization signal to the FPGA time synchronization unit, The other GPS second pulse signal and line/frame synchronization signal are sent to the space stereo surveying and mapping camera controller through the second pulse and line/frame synchronization signal output cable, and enter step D;

Step D, the FPGA time synchronization unit constructs three counters inside the FPGA, the row/frame synchronization counter generates the row/frame number by counting the falling edge of the row/frame synchronization signal, and the second counter generates the system time by counting the falling edge of the GPS second pulse The second value, the microsecond counter counts the rising edge of the clock signal generated by the high-stability crystal oscillator to obtain the microsecond value of the system time; when the system is reset, the initial value of the second counter value and the microsecond counter value is set to 0, and the line/ The initial value of the frame synchronization counter is 1; the value of the microsecond counter is cleared on the falling edge of the GPS second pulse to complete time synchronization; the rising edge of the line/frame synchronization signal is used to set the line/frame synchronization counter value, the second counter value and the microsecond value The second counter value is latched to generate a set of FPGA time synchronization data consisting of row/frame number, second value and microsecond value corresponding to the row/frame; FPGA time synchronization data and row/frame synchronization signal are delayed to generate data transmission The trigger signal is sent to the data acquisition card, and step E is entered;

Step E, the bus communication card receives the image time synchronization information sent by the camera controller to the imaging unit of the spatial three-dimensional surveying and mapping camera through the bus monitoring cable, and sends it to the data processing computer system; the data acquisition card sends the collected FPGA time synchronization data to the data processing Computer system, enter step F;

Step F, data processing The computer system receives the FPGA timing data sent by the data acquisition card and stores it on the hard disk in the form of a file, and simultaneously receives the image timing information sent by the bus communication card and stores it on the hard disk in the form of a file; data processing The software reads the image time synchronization information and FPGA time synchronization data from the hard disk, compares the difference between the second value and the microsecond value corresponding to the same line/frame number in the image time synchronization information and FPGA time synchronization data, and obtains the camera time corresponding to this line Synchronization error, camera time synchronization error data is recorded in the hard disk and displayed in the form of curves.

Beneficial effects of the present invention:

1. By dividing the second pulse and line/frame synchronization signal into two after switching, the measurement process will not affect the normal operation of the spatial stereoscopic mapping camera, so that it can truly record the time sequence of the camera controller during the working process. Changes the dynamics of camera time synchronization errors.

2. Since the FPGA time synchronization data and image time synchronization data are stored in the hard disk, the FPGA time synchronization unit as a reference always maintains high accuracy in measurement, which can overcome the limitations of conventional instruments such as logic analyzers due to the limitation of storage depth. Long-term detection of shortcomings with a high sampling frequency, to achieve full-scale measurement of camera time synchronization accuracy during the photography process of the spatial three-dimensional mapping camera.

3. By monitoring the bus, the image timing information is directly received from the internal bus, which can significantly reduce the time for separating image data and extracting image timing information. Regularly write the latest image timing information and FPGA timing data to the hard disk, forming a new file each time. The size of the file is fixed and small, so that the data processing software can quickly compare and calculate, so that spatial three-dimensional mapping can be realized Real-time measurement, recording and display of camera time synchronization accuracy.

Description of drawings

FIG. 1 is a schematic structural diagram of a whole-process real-time detection system for time synchronization precision of a spatial stereoscopic mapping camera according to the present invention.

FIG. 2 is a flow chart of the whole process real-time detection method for the time synchronization accuracy of the spatial stereoscopic mapping camera described in the second specific embodiment.

FIG. 3 is a timing simulation diagram of the FPGA time synchronization unit in the second embodiment.

Detailed ways

Specific Embodiments 1. This embodiment is described in conjunction with FIG. 1 . The whole-process real-time detection system for the time synchronization accuracy of a spatial three-dimensional surveying and mapping camera consists of a second pulse and line/frame synchronization signal input cable 10 , and a second pulse and line/frame synchronization signal conversion unit 20 , pulse per second and line/frame synchronization signal output cable 50, FPGA timing unit 30, data acquisition card 40, bus monitoring cable 60, bus communication card 70 and data processing computer system 80.

Described second pulse and line/frame synchronous signal input cable 10 are made up of GPS second pulse cable and line/frame synchronous signal cable, in the present embodiment GPS second pulse cable connects ground GPS simulation equipment and second pulse and line/frame synchronous signal The conversion unit 20 transmits the GPS second pulse signal; the line/frame synchronization signal cable connects the spatial stereoscopic mapping camera imaging unit and the second pulse and line/frame synchronization signal conversion unit 20, and transmits the line/frame sent by the spatial stereoscopic mapping camera imaging unit synchronization signal;

Second pulse and row/frame synchronous signal transfer unit 20 and second pulse and row/frame synchronous signal input cable 10 are connected, receive GPS second pulse signal and row/frame synchronous signal and divide into two, one of them GPS second pulse signal And the line/frame synchronization signal is sent to the FPGA time synchronization unit 20, and the other GPS second pulse signal and the line/frame synchronization signal are sent to the second pulse and line/frame synchronization signal output cable 50; the second pulse and line/frame synchronization signal output cable 50 send the second pulse and line/frame synchronization signal back to the camera controller of the spatial stereo mapping camera;

FPGA time synchronization unit 30 is made up of level conversion chip 31, FPGA32 and high-stability crystal oscillator 33, and level conversion chip 31 converts GPS second pulse signal and line/frame synchronization signal into the TTL level signal commonly used by FPGA32; In addition to the GPS second pulse signal and line/frame synchronization signal after level conversion, the clock signal generated by the high-stability crystal oscillator 33 is also received; FPGA32 generates FPGA time synchronization data according to the GPS second pulse signal, line/frame synchronization signal and clock signal, Each line generates a group of FPGA timing data and data sending trigger signals, which are sent to the data acquisition card 40;

In the present embodiment, the second pulse and the line/frame synchronization signal are transmitted using the low-voltage differential signal (LVDS) standard, and the level conversion chip 31 adopts SN55LVDS32 to convert the second pulse and the line/frame synchronization signal from LVDS level to TTL level. FPGA32 adopts XCV300 with 300,000 gates of Xilinx Company, and high-stability crystal oscillator 33 adopts a temperature-compensated crystal oscillator with a frequency of 10MHz and a frequency difference of 1PPM.

Data acquisition card 40 is connected with FPGA timing unit 30, receives data and sends trigger signal and FPGA timing data, data acquisition card 40 is installed in the motherboard slot of data processing computer, and the FPGA timing data received is sent to data processing computer system 80 . In this embodiment, the data acquisition card 40 adopts the PCI7300A of ADLINK, and is installed in the PCI slot of the main board of the data processing computer. The maximum acquisition bit width of the data acquisition card is 32 bits.

The bus monitoring cable 60 is connected on the communication bus between the imaging unit of the spatial stereo surveying and mapping camera and the camera controller, receives the image timing information sent by the camera controller to the imaging unit, and sends it to the bus communication card 70; the bus communication card 70 communicates with the The bus monitoring cable 60 connected thereto receives image timing information.

The communication bus between the imaging unit of the spatial stereoscopic surveying and mapping camera and the controller of the spatial stereoscopic surveying and mapping camera is a 485 bus with a baud rate of 31.25kbps; the bus communication card 70 adopts the multi-serial port card CP134U of MOXA Company, and is installed in the data processing computer 80 In the PCI slot of the motherboard, the received image timing information is sent to the data processing computer system 80;

Described data processing computer system 80 is made up of data processing computer, data receiving and storing software and data processing software, and data processing computer system 80 is connected with data acquisition card 40 and bus communication card 70, receives the FPGA time synchronization that data acquisition card 40 transmits The image time synchronization information transmitted by the data and bus communication card 70 is stored on the hard disk in the form of a file; the data processing software reads the image time synchronization information and the FPGA time synchronization data from the hard disk, and calculates the corresponding camera time synchronization error of each line , the calculation results are recorded in the hard disk, and can be displayed in real time in the form of curves.

In this embodiment, the hard disk capacity of the data processing computer is 500G, and the free space available for testing is 300G.

In this embodiment, usually, multiple signals in the interface between the imaging unit of the spatial stereoscopic surveying and mapping camera and the controller of the spatial stereoscopic surveying and mapping camera are output through a connector, that is, the connector contains other control signals in addition to the line synchronization signal. In this case, in order to be consistent with the connector, the second pulse and line/frame synchronization signal input cable and the second pulse and line/frame synchronization signal output cable transmit other signals in addition to the second pulse and line/frame synchronization signal, the other The signal can be a period signal, a clock signal and a reset signal. The second pulse and line/frame synchronization signal conversion unit does not divide the second pulse and line/frame synchronization signal into two, but directly outputs them.

Specific embodiment two, illustrate present embodiment in conjunction with Fig. 2 and Fig. 3, the whole process real-time detection method of time synchronization accuracy of spatial stereo surveying and mapping camera, this method is realized by the following steps:

In step A, the GPS emulation device and the cable between the imaging unit and the camera controller are replaced with the pulse-per-second and line/frame synchronization signal input cable 10 and the pulse-second and line/frame synchronization signal output cable 50 . The specific process is to disconnect the GPS second pulse connection cable between the GPS simulation device and the camera controller, disconnect the cable containing the line/frame synchronization signal between the imaging unit and the camera controller; connect the second pulse to the line/frame synchronization signal The input end of input cable 10 is connected in the second pulse output interface of GPS simulation equipment and the line/frame synchronous signal output interface of imaging unit; On the frame synchronization signal switching unit; the input end of the second pulse and the line/frame synchronization signal output cable 50 is connected on the second pulse and the line/frame synchronization signal switching unit, and the second pulse and the line/frame synchronization signal output cable 50 The output end is connected to the second pulse and line/frame synchronization signal input interface of the camera controller, and enters step B.

In step B, the FPGA timing unit 30 is reset, the time scale value that the GPS simulation device is set to send to the space stereo surveying and mapping camera and the number of second pulses sent to the second pulse and line/frame synchronization signal switching unit 20 one by one Correspondingly, the GPS emulation device then starts to send the GPS second pulse and time stamp, and enters step C.

In step C, the second pulse and line/frame synchronization signal switching unit 20 divides the GPS second pulse signal and the line/frame synchronization signal into two, and sends one of the GPS second pulse signal and the line/frame synchronization signal to the FPGA Time synchronization unit 30, another GPS second pulse signal and line/frame synchronization signal are sent to the camera controller through the second pulse and line/frame synchronization signal output cable, and enter step D.

In step D, FPGA time unit 30 constructs three counters inside FPGA31 namely XCV300, and the counters are all 32 bits; the line/frame synchronous counter generates line/frame number to the falling edge count of line/frame synchronous signal, and the second counter The falling edge count of the GPS second pulse generates the second value of the system time, and the microsecond counter counts the rising edge of the clock signal generated by the high-stability temperature-compensated crystal oscillator to obtain the microsecond value of the system time; when the system is reset, the second counter value and The initial value of the microsecond counter value is 0, and the initial value of the line/frame synchronization counter is set to 1; the value of the microsecond counter is cleared on the falling edge of the GPS second pulse to complete time synchronization; the rising edge of the line/frame synchronization signal is used Latch the row/frame synchronization counter value, second counter value and microsecond counter value to generate a set of FPGA time synchronization data consisting of row/frame number, second value and microsecond value corresponding to the row. Delay the line/frame synchronization signal to generate a data sending trigger signal, send it to the data acquisition card 40 together with the FPGA time synchronization data, and enter step E.

In this embodiment, since the data acquisition card 40 adopts PCI7300A, the maximum acquisition bit width is 32 bits, and the line/frame synchronization counter, second counter and microsecond counter are all 32 bits, so each group of FPGA time synchronization data needs to be divided into three times Output, corresponding to generate three data sending trigger signals as the output clock, Figure 3 is the FPGA timing simulation diagram, the output data is sequentially output as the row number, second value and microsecond value.

In step E, the bus communication card 70, that is, the CP134U, receives the image time synchronization information sent by the camera controller to the imaging unit through the bus monitoring cable 60, and sends it to the data processing computer system 80; the data acquisition card 40 collects the FPGA time synchronization data Send to the data processing computer system 80, enter step F.

In step F, data processing computer system 80 receives FPGA timing data and image timing information from data acquisition card 40 and bus communication card 70 respectively; The time synchronization information is written to the hard disk once, and each write forms a new FPGA time synchronization data file and image time synchronization information file. The data processing software reads the latest FPGA time synchronization data file and image time synchronization information file every 10 seconds. Compare the difference between the second value and the microsecond value corresponding to the same line/frame number in the image time synchronization information and the FPGA time synchronization data, and obtain the camera time synchronization error corresponding to the line, which is displayed in real time and recorded in the hard disk.

In the present embodiment, during the photographing process, the data processing computer system 80 writes the newly received FPGA time synchronization data and image time synchronization information to the hard disk once every time, and writes each time to form a new FPGA time synchronization data file and Image time synchronization information file, data processing software regularly reads the latest FPGA time synchronization data file and image time synchronization information file, after comparison and calculation, the camera time synchronization error of the corresponding line is obtained, displayed in real time and recorded in the hard disk. The reading frequency of the FPGA time synchronization data file and the image time synchronization information file is at least twice the writing frequency to ensure that no data is missed.

In the present invention, in order to realize the real-time measurement of the time synchronization accuracy of the spatial stereoscopic mapping camera in the working process, at first the second pulse and the row/frame synchronization signal input cable 10 and the second pulse and the row/frame synchronization signal switching unit convert the second pulse The line/frame synchronization signal is divided into two, and one line is sent to the camera controller through the second pulse and line/frame synchronization signal output cable to ensure the normal operation of the spatial three-dimensional mapping camera, and the other line is sent to the FPGA time synchronization unit to generate FPGA time synchronization data. Since the FPGA time synchronization unit uses a high-stability crystal oscillator as the clock source, it only receives the second pulse and the line/frame synchronization signal, and uses a pure hardware sequential circuit to detect the edge of the line synchronization signal and the GPS second pulse signal to generate time synchronization data. Due to the influence of other tasks, time synchronization errors are introduced into the process of time synchronization, timekeeping and time use, and there are no time synchronization errors caused by software fetching and decoding during execution, and cameras that need to complete complex tasks such as image motion calculations at the same time Compared with the controller, it has much higher time synchronization accuracy and stability.

Since the time synchronization error of the FPGA time synchronization unit is very small and basically unchanged, it can be calibrated with a logic analyzer. The time difference of the same line/frame number in the data can get the camera time synchronization error.

Since the camera time synchronization accuracy is finally reflected in the image timing information inserted into the image auxiliary data, and each line/frame of image auxiliary data is sent to the digital transmission interface together with the line/frame image data, since the image data is more accurate than the image auxiliary data The amount of data is much larger. If the image timing information in the image auxiliary data is received and extracted from the digital transmission interface through the Kuaisai computer, it will take a lot of time to separate the image auxiliary data from the massive image data, and then extract the image pair. real-time information, it is difficult to meet the real-time requirements. Since the camera controller generates the image timing information and sends it to the imaging unit through the internal bus, in the present invention, the bus monitoring cable and the bus communication card directly receive the image timing information from the internal bus, which can significantly reduce the number of separate image data and image extraction. The time of the time information.

Since the spatial stereo mapping camera may take pictures for tens of minutes or even several hours, when conventional instruments such as logic analyzers or oscilloscopes are used to measure the time synchronization accuracy, due to insufficient storage depth, it is difficult to detect for a long time with a high sampling frequency. In the present invention, since the image time synchronization information and the FPGA time synchronization data as a comparison reference are all stored in the hard disk, long-term measurement can be performed while keeping the measurement accuracy unchanged. Taking a hard disk with 200G free space as an example, it can measure continuously for thousands of hours while keeping the measurement accuracy unchanged.

Since the data processing software reads the image time synchronization information and FPGA time synchronization data stored in the form of files from the hard disk, if the image time synchronization information and FPGA time synchronization data are stored in the form of a single file, as the camera shooting time increases, the file The continuous increase of the size will lead to the continuous increase of the time for reading, searching and comparing the image time synchronization information and FPGA time data, and it is difficult to realize the real-time calculation and display of the camera time synchronization error. In the present invention, the latest image timing information and FPGA timing data are regularly written into the hard disk, and a new file is formed each time. The size of the file is fixed and small, so that the data processing software can compare and calculate quickly. In order to ensure that no data is missed, in the present invention, the reading frequency of the FPGA time synchronization data file and the image time synchronization information file is at least twice the writing frequency.

The present invention can be used for testing the camera's time synchronization accuracy in the whole satellite state. At this time, the second pulse and line/frame synchronization signal input cable 10 receives the GPS second pulse signal sent by the GPS receiver on the satellite. The present invention can also be used for the test of camera time synchronization accuracy when only the camera subsystem is used. At this time, the second pulse and line/frame synchronization signal input cable 10 receives the GPS second pulse signal sent by the GPS simulation equipment for ground testing.

As described above, those skilled in the art can make various changes and modifications in the form and details of this embodiment without departing from the principle of the present invention, and these changes and modifications are all determined to be included in the within the scope of the present invention.

Claims (7)

1. A whole-process real-time detection system for the time synchronization accuracy of a spatial three-dimensional surveying and mapping camera, the system includes an input cable (10) for the second pulse and line/frame synchronization signal, a switching unit (20) for the second pulse and the line/frame synchronization signal, and a second pulse Pulse and line/frame synchronization signal output cable (50), FPGA time synchronization unit (30), data acquisition card (40), bus monitoring cable (60), bus communication card (70) and data processing computer system (80); It is characterized by, The second pulse is connected with the line/frame synchronization signal input cable (10) and the second pulse and the line/frame synchronization signal conversion unit (20), and the second pulse and the line/frame synchronization signal conversion unit (20) receives the second Pulse and line/frame synchronization signal input cable (10) input GPS second pulse signal and line/frame synchronization signal, and GPS second pulse signal and line/frame synchronization signal are divided into two paths, one road GPS second pulse signal and line/frame synchronization signal The frame synchronization signal is sent to the FPGA timing unit (30), and another GPS second pulse signal and the line/frame synchronization signal are sent to the second pulse and the line/frame synchronization signal output cable (50); the second pulse is synchronized with the line/frame synchronization signal The signal output cable (50) transmits the GPS second pulse signal and line/frame synchronization signal to the spatial stereo surveying and mapping camera controller; Described FPGA timing unit (30) is connected with data acquisition card (40), and FPGA timing unit (30) is made up of level conversion chip (31), FPGA (32) and high-stability crystal oscillator (33), level Conversion chip (31) converts GPS second pulse signal and line/frame synchronous signal into TTL level signal; Described FPGA (32) receives the clock signal that TTL level signal and high stability crystal oscillator (33) produce; FPGA (32 ) produce FPGA time synchronization data according to GPS second pulse signal, line/frame synchronization signal and clock signal, each row produces a group of FPGA time synchronization data and data sending trigger signal, and described FPGA time synchronization unit (30) FPGA time synchronization data and the data sending trigger signal is sent to the data acquisition card (40); Said data acquisition card (40) receives the FPGA timing data and data sending trigger signal sent by the FPGA timing unit (30), and sends to the data processing computer system (80); The bus monitoring cable (60) is connected to the communication bus between the spatial stereo surveying and mapping camera imaging unit and the spatial stereo surveying and mapping camera controller, and the bus monitoring cable (60) receives the spatial stereo surveying and mapping camera controller and sends it to the spatial stereo surveying and mapping camera for imaging The image timing information of the unit is sent to the bus communication card (70); The bus communication card (70) receives the image timing information transmitted by the bus monitoring cable (60), and transmits the received image timing information to the data processing computer system (80); Described data processing computer system (80) is connected with data acquisition card (40) and bus communication card (70), and data processing computer system (80) is made up of data processing computer, data receiving storage software and data processing software, and described data Processing computer and data receiving storage software receive the FPGA timing data that data acquisition card (40) transmits and the image timing information that bus communication card (70) transmits is stored on the hard disk with the form of file; Described data processing software is from hard disk Read the image time synchronization information and FPGA time synchronization data, calculate the camera time synchronization error corresponding to each row, record the obtained results in the hard disk, and display them in real time in the form of curves. 2. the whole process real-time detection system of the time synchronization accuracy of the space three-dimensional surveying and mapping camera according to claim 1, is characterized in that, described second pulse and line/frame synchronous signal input cable (10) receive the GPS that the GPS receiver on the satellite sends The second pulse signal or the GPS second pulse signal sent by the GPS simulation equipment for ground testing, and the received GPS second pulse signal is sent to the second pulse and line/frame synchronization signal conversion unit (20). 3. The whole process real-time detection system of the time synchronization accuracy of the spatial three-dimensional surveying and mapping camera according to claim 1, characterized in that, the second pulse and line/frame synchronization signal input cable (10) and the second pulse and line/frame synchronization signal The output cable (50) transmits the line period signal, clock signal and reset signal except the GPS second pulse signal and line/frame synchronization signal, and passes through the second pulse and line/frame synchronization signal conversion unit (20) and the second pulse and line The frame synchronization signal output cable (50) is directly output to the spatial stereo surveying and mapping camera controller. 4. The whole process real-time detection system of the time synchronization accuracy of the spatial three-dimensional surveying and mapping camera according to claim 1, characterized in that, the second pulse and line/frame synchronization signal input cable (10) is composed of GPS second pulse cable and line/frame Composed of synchronization signal cables, the GPS second pulse cable transmits the GPS second pulse signal sent by the GPS receiver on the satellite or the GPS simulation device for ground testing; the line/frame synchronization signal cable receives the line/frame synchronization sent by the imaging unit of the spatial stereoscopic surveying and mapping camera Signal. 5. the whole process real-time detection system of spatial three-dimensional surveying and mapping camera time synchronization precision according to claim 1, it is characterized in that, described data acquisition card (40) is installed in the motherboard slot of data processing computer, bus communication card (70 ) is installed in the motherboard slot of the data processing computer or connected to the USB port of the data processing computer. 6. The whole process real-time detection method of the time synchronization accuracy of the spatial three-dimensional surveying and mapping camera, which is characterized in that the method is realized by the following steps: Step A, disconnect the GPS second pulse connection cable between the GPS receiver or GPS simulation device and the spatial stereoscopic mapping camera controller, and disconnect the line/frame synchronization signal between the spatial stereoscopic mapping imaging unit and the spatial stereoscopic mapping camera controller The cable of the second pulse and line/frame synchronization signal input cable (10) is connected to the line/frame synchronization signal output interface of the GPS second pulse output interface of the GPS receiver or the GPS emulation device and the spatial three-dimensional surveying and mapping imaging unit; Connect the output end of the second pulse and line/frame sync signal input cable (10) to the second pulse and line/frame sync signal transfer unit (20); the second pulse and line/frame sync signal output cable (50) input end is connected on the second pulse and line/frame synchronous signal transition unit (20), the output end of the second pulse and line/frame synchronous signal output cable (50) is connected on the second pulse and line/ On the frame synchronization signal input interface, go to step B; Step B, the FPGA timing unit (30) is reset, the GPS receiver or GPS emulation equipment is set and sent to the time scale value of the spatial stereo surveying and mapping camera controller and sent to the second pulse and line/frame synchronization signal switching unit (20 ) corresponding to the number of pulses per second, then the GPS receiver or GPS simulation device starts to send the pulse per second of GPS and the time scale value, and enters step C; Step C, second pulse and line/frame synchronous signal transfer unit (20) divide GPS second pulse signal and line/frame synchronous signal into two paths, send the GPS second pulse signal and line/frame synchronous signal to FPGA pair wherein Time unit (30), another GPS second pulse signal and line/frame synchronization signal are sent to the space stereo surveying and mapping camera controller through the second pulse and line/frame synchronization signal output cable (50), and enter step D; Step D, FPGA time synchronization unit (30) constructs three counters inside FPGA (32), row/frame synchronous counter generates row/frame number to the falling edge counting of row/frame synchronous signal, second counter falls to GPS second pulse The second value of the system time is generated by counting along the edge, and the microsecond counter counts the rising edge of the clock signal generated by the high stability crystal oscillator (33) to obtain the microsecond value of the system time; when the system is reset, the second counter value and the microsecond counter value are set The initial value of the line/frame synchronization counter is 0, and the initial value of the line/frame synchronization counter is 1; the value of the microsecond counter is cleared on the falling edge of the GPS second pulse, and the time synchronization is completed; the line/frame is set on the rising edge of the line/frame synchronization signal The synchronous counter value, the second counter value and the microsecond counter value are latched to generate a set of FPGA time synchronization data consisting of the row/frame number, the second value and the microsecond value corresponding to the row/frame; the FPGA time synchronization data and row After the delay of the / frame synchronization signal, the data transmission trigger signal is generated and sent to the data acquisition card (40), and enters step E; Step E, the bus communication card (70) receives the image timing information sent by the camera controller to the imaging unit of the spatial three-dimensional surveying and mapping camera through the bus monitoring cable (60), and sends it to the data processing computer system (80); the data acquisition card (40) The FPGA timing data collected is sent to the data processing computer system (80), and enters step F; Step F, the data processing computer system (80) receives the FPGA timing data sent by the data acquisition card (40) and stores it on the hard disk in the form of a file, and simultaneously receives the image timing information sent by the bus communication card (70) and sends it as a file. stored on the hard disk; the data processing software reads the image time synchronization information and FPGA time synchronization data from the hard disk, and compares the second value and microsecond value corresponding to the same row/frame number in the image time synchronization information and FPGA time synchronization data difference, get the camera time synchronization error corresponding to this row, and the camera time synchronization error data is recorded in the hard disk and displayed in the form of a curve. 7. the full-scale real-time detection method of time synchronization precision of spatial three-dimensional surveying and mapping camera according to claim 6, is characterized in that, in photographing process, data processing computer system (80) is with the newly received FPGA time synchronization data at regular intervals and image time synchronization information are written to the hard disk once, each writing forms a new FPGA time synchronization data file and image time synchronization information file, and the data processing software regularly reads the latest FPGA time synchronization data file and image time synchronization information file, After comparison and calculation, the camera time synchronization error of the corresponding line is displayed and recorded in the hard disk in real time; the reading frequency of the FPGA time synchronization data file and the image time synchronization information file is twice the writing frequency.

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