CN102222477A - Grid driving method, grid driving circuit and pixel structure - Google Patents

Abstract

The invention relates to a gate driving method, a gate driving circuit and a pixel structure, wherein the gate driving method includes: applying a first gate driving voltage to the gate of a pixel whose data driving voltage is a positive polarity signal, A second gate driving voltage is applied to the gate of the pixel whose voltage is a negative polarity signal, and the first gate driving voltage is higher than the second gate driving voltage. The present invention satisfies the charging requirements of the pixel electrodes for positive or negative signals by loading different gate drive voltages on the gates of pixels with positive or negative signals; Applying a second gate drive voltage with a lower voltage effectively alleviates the problem of TFT gate bias and prolongs the service life of TFT; compared with the prior art, the power consumed by loading the second gate drive voltage Smaller, saving the power consumption of the LCD panel.

Description

Gate driving method, gate driving circuit and pixel structure

technical field

The invention relates to liquid crystal display technology, in particular to a grid driving method, a grid driving circuit and a pixel structure.

Background technique

In the current traditional liquid crystal display, in order to prevent the aging phenomenon of the liquid crystal in the DC state for a long time, the data driving voltage provided by the data line to the pixel electrode is an AC signal. When the data driving voltage is higher than the common electrode voltage, the data driving voltage is called is a positive polarity signal, and when the data driving voltage is lower than the common electrode voltage, the data driving voltage is called a negative polarity signal.

In a traditional liquid crystal display, no matter what kind of driving method is adopted, when the pixel of the thin film transistor (Thin Film Transistor, referred to as: TFT) is turned on, no matter whether the data driving voltage is a positive polarity signal or a negative polarity signal, it is loaded on the gate of the TFT gate. The drive voltage is a high voltage signal. If a higher gate drive voltage is applied to the TFT of the pixel electrode of the negative polarity signal for a long time, the higher TFT gate bias will reduce the service life of the TFT, resulting in earlier, faster and larger TFT offset; and, unnecessary power consumption of the liquid crystal panel is also increased.

Contents of the invention

The invention provides a gate driving method, a gate driving circuit and a pixel structure, which are used to improve the service life of TFTs and save the power consumption of liquid crystal panels.

The present invention provides a gate driving method, comprising:

The first gate driving voltage is applied to the gate of the pixel whose data driving voltage is a positive polarity signal, and the second gate driving voltage is applied to the gate of a pixel whose data driving voltage is a negative polarity signal, and the first gate The driving voltage is higher than the second gate driving voltage.

The present invention provides a gate driving circuit, comprising: a loading circuit for loading a first gate driving voltage on the gate of a pixel whose data driving voltage is a positive polarity signal, and a pixel whose data driving voltage is a negative polarity signal Loading a second gate driving voltage on the gate;

The first gate driving voltage is higher than the second gate driving voltage.

The present invention provides a pixel structure, which includes at least one row of pixels, and further includes: two gate signal lines for driving the row of pixels; the two gate signal lines are respectively used for applying a first gate driving voltage and a second gate drive voltage, the first gate drive voltage being higher than the second gate drive voltage;

The gate signal line loaded with the first gate drive voltage is used to drive the pixels whose data drive voltage is a positive signal in the row of pixels; the gate signal line loaded with the second gate drive voltage is used to drive the row of pixels The middle data driving voltage is a pixel with a negative polarity signal.

The present invention satisfies the charging requirements of the pixel electrodes for positive or negative signals by loading different gate drive voltages on the gates of pixels with positive or negative signals; Applying a second gate drive voltage with a lower voltage effectively alleviates the TFT gate bias problem and prolongs the service life of the TFT; compared with the prior art, the power consumed by loading the second gate drive voltage Smaller, saving the power consumption of the LCD panel.

Description of drawings

FIG. 1 is a flowchart of an embodiment of the gate driving method of the present invention;

FIG. 2 is a schematic structural diagram of Embodiment 2 of the gate drive circuit of the present invention;

3 is a schematic structural diagram of Embodiment 3 of the gate drive circuit of the present invention;

FIG. 4 is a schematic structural diagram of Embodiment 4 of the gate drive circuit of the present invention;

FIG. 5 is a structural schematic diagram of Embodiment 1 of the pixel structure of the present invention;

FIG. 6 is a schematic structural diagram of Embodiment 2 of the pixel structure of the present invention.

Detailed ways

The technical solutions of the present invention will be described in further detail below with reference to the accompanying drawings and embodiments.

FIG. 1 is a flowchart of an embodiment of a gate driving method of the present invention. As shown in Figure 1, this embodiment includes the following parts:

101. Apply a first gate driving voltage to the gate of a pixel whose data driving voltage is a positive polarity signal;

102. Apply a second gate driving voltage to a gate of a pixel whose data driving voltage is a negative polarity signal.

Wherein the first gate driving voltage is higher than the second gate driving voltage.

After research, it is found that under the same gate driving voltage, the charging time required for positive and negative polarity signals will be different, and the charging time for positive polarity signals is longer than that for negative polarity signals. The gate driving method provided in this embodiment utilizes this research achievement, and applies a second gate driving voltage with a lower voltage to the gate of the pixel whose data driving voltage is a negative polarity signal, and appropriately prolongs the negative polarity compared with the prior art. The charging time of signal pixels does not require a very high gate driving voltage to well meet the charging requirements of negative polarity signal pixels.

The gate driving method provided in this embodiment can be applied to various driving modes, which are described below:

(1) Applied to the frame inversion driving method

In the frame inversion driving mode, if the data driving voltage provided by the data line to the pixels of the current frame is a positive signal, the data driving voltage provided by the data line to the next frame of pixels is a negative signal, that is, for each For a frame image signal, the data driving voltage provided by the data line to the pixel is either a positive polarity signal or a negative polarity signal. .

If the data driving voltage of the pixels in the current frame is a positive polarity signal, apply the first gate driving voltage to the gates of the pixels in the current frame to fully charge the pixel electrodes in the current frame; the data driving voltage of the pixels in the next frame is a negative polarity signal , applying the second gate driving voltage to the gates of the pixels in the next frame, so that the pixel electrodes in the next frame are fully charged.

In the frame inversion driving mode, through the high and low voltage conversion of the above-mentioned gate driving voltage with the frame inversion, the charging requirements of the pixel electrode of the positive polarity signal or the negative polarity signal are met; A second gate drive voltage with a lower voltage is applied to the electrode, which effectively alleviates the problem of TFT gate bias and prolongs the service life of the TFT; compared with the prior art, the energy consumed by loading the second gate drive voltage The power is small, which saves the power consumption of the LCD panel.

(2) Applied to row inversion driving mode

In the row inversion driving mode, for a certain frame of image signal, if the data driving voltage provided by the data line to the pixels in the nth row is a positive signal, the data driving voltage provided by the data line to the pixels in the n+1th row It is a negative polarity signal; for the next frame of this frame of image signal, the data driving voltage provided by the data line to the nth row of pixels is a negative polarity signal, and the data driving voltage provided by the data line to the n+1th row of pixels is positive sexual signal.

If the data driving voltage of a certain row of pixels of a certain frame of image signal is a positive polarity signal, the first gate driving voltage is applied to the grid of this row of pixels to fully charge the row of pixel electrodes; the data driving voltage of the next row of pixels The voltage is a signal of negative polarity, and the second gate driving voltage is applied to the gates of the next row of pixels, so that the electrodes of the next row of pixels are fully charged.

In the row inversion driving mode, through the above-mentioned high-low voltage conversion of the gate driving voltage following the row and frame inversion, the charging requirements of the pixel electrodes of the positive polarity signal or the negative polarity signal are met; A second gate drive voltage with a lower voltage is applied to the gate, which effectively alleviates the problem of TFT gate bias and prolongs the service life of the TFT; compared with the prior art, the second gate drive voltage applied The power consumption is small, which saves the power consumption of the liquid crystal panel.

(3) Applied to 1 dot (Dot) interlaced inversion drive mode

In the 1-dot interlaced inversion driving method, for a certain frame of image signal, if the data drive voltage provided by the data line to the pixels in the nth row of odd columns is a positive polarity signal, then the data line is provided to the pixels in the nth row of even columns. The data driving voltage provided by the data line is a negative polarity signal, the data driving voltage provided by the data line to the pixels in the odd-numbered column of the n+1th row is a negative polarity signal, and the data driving voltage provided by the data line to the pixels in the even-numbered column of the n+1th row is a positive polarity signal ; For the next frame of this frame of image signal, the data drive voltage provided by the data line to the pixels in the nth row of odd columns is a negative polarity signal, and the data drive voltage provided by the data line to the pixels in the nth row of even columns is a positive polarity signal , the data driving voltage provided by the data line to the pixels in the odd-numbered column of the n+1th row is a positive polarity signal, and the data driving voltage provided by the data line to the pixels in the even-numbered column of the n+1th row is a negative polarity signal.

Conversely, for a certain frame of image signal, if the data drive voltage provided by the data line to the pixels in the odd-numbered column of the nth row is a negative polarity signal, then the data driving voltage provided by the data line to the pixels in the even-numbered column of the nth row is a positive polarity signal , the data driving voltage provided by the data line to the pixels in the odd-numbered row of the n+1th row is a positive polarity signal, and the data driving voltage provided by the data line to the pixels in the even-numbered column of the n+1th row is a negative polarity signal; For one frame, the data driving voltage provided by the data line to the pixels in the odd-numbered column of the nth row is a positive polarity signal, and the data driving voltage provided by the data line to the pixels in the even-numbered column of the nth row is a negative polarity signal, and the data line is provided to the n+th row The data driving voltage of the odd-numbered column pixels in one row is a negative polarity signal, and the data driving voltage provided by the data line to the n+1th row of even-numbered column pixels is a positive polarity signal.

If the data driving voltage of a pixel in a certain row and a certain column of a certain frame of image signal is a positive polarity signal, load the first gate driving voltage on the gate of the pixel to fully charge the pixel electrode; if a certain frame of image signal The data driving voltage of a pixel in a certain row and a certain column is a negative polarity signal, and a second gate driving voltage is applied to the gate of the pixel to fully charge the pixel electrode.

In the 1-point interlaced inversion driving mode, by loading different gate driving voltages on the gates of the pixels with positive polarity signals and negative polarity signals, the charging requirements of the pixel electrodes with positive polarity signals or negative polarity signals are met; at the same time, in A second gate drive voltage with a lower voltage is applied to the gate of the pixel with a negative polarity signal, which effectively alleviates the problem of TFT gate bias and prolongs the service life of the TFT; compared with the prior art, the second The gate driving voltage consumes less power, which saves the power consumption of the liquid crystal panel.

(4) Applied to 2-dot (Dot) interlaced reverse drive mode

In the 2-dot interlaced inversion driving method, it is assumed that each row of pixels is divided into multiple groups, and each group includes 2 adjacent pixels. For a certain frame of image signal, if the data line is provided to the odd The data driving voltage of the group of pixels is a positive polarity signal, then the data driving voltage provided by the data line to the nth row of even group pixels is a negative polarity signal, and the data driving voltage provided by the data line to the n+1th row of odd group pixels is a negative polarity signal signal, the data drive voltage provided by the data line to the even group of pixels in the n+1 row is a positive polarity signal; for the next frame of this frame of image signal, the data drive voltage provided by the data line to the odd group of pixels in the nth row is Negative polarity signal, the data driving voltage provided by the data line to the even group of pixels in the nth row is a positive polarity signal, and the data driving voltage provided by the data line to the odd group of pixels in the n+1th row is a positive polarity signal, and the data line is provided to the nth row The data driving voltage of the even group of pixels in the +1 row is a negative polarity signal.

Conversely, for a certain frame of image signal, if the data driving voltage provided by the data line to the pixels in the nth row of odd groups is a negative polarity signal, then the data driving voltage provided by the data line to the pixels in the nth row of even groups is a positive polarity signal , the data drive voltage provided by the data line to the n+1th row of odd-group pixels is a positive polarity signal, and the data drive voltage provided by the data line to the n+1th row of even-group pixels is a negative polarity signal; for the next frame of image signal For one frame, the data drive voltage provided by the data line to the pixels in the nth row of odd groups is a positive polarity signal, the data drive voltage provided by the data line to the pixels in the nth row of even groups is a negative polarity signal, and the data line is provided to the n+th row The data driving voltage of the odd group of pixels in the first row is a negative polarity signal, and the data driving voltage provided by the data line to the n+1th row of the even group of pixels is a positive polarity signal.

If the data driving voltage of a certain group of pixels in a certain row of a certain frame of image signal is a positive polarity signal, the first gate driving voltage is applied to the grid of the group of pixels to fully charge the pixel electrode; if a certain frame The data driving voltage of a certain group of pixels in a certain row of the image signal is a negative polarity signal, and the second gate driving voltage is applied to the gate of the group of pixels to fully charge the pixel electrode.

In the 2-point interlaced inversion driving mode, by loading different gate driving voltages on the gates of the pixels with positive polarity signals and negative polarity signals, the charging requirements of the pixel electrodes with positive polarity signals or negative polarity signals are met; at the same time, in A second gate drive voltage with a lower voltage is applied to the gate of the pixel with a negative polarity signal, which effectively alleviates the problem of TFT gate bias and prolongs the service life of the TFT; compared with the prior art, the second The gate driving voltage consumes less power, which saves the power consumption of the liquid crystal panel.

Similar to the above-mentioned 2-dot interlaced inversion driving method, this embodiment can also be used in a multi-dot (greater than 2 dots) interlaced inversion driving method, wherein each row of pixels is divided into multiple groups, and each group includes more than 3 adjacent pixels.

For the above-mentioned various driving methods, the present invention also provides corresponding gate driving circuits, which are described in detail as follows.

Embodiment 1 of the gate drive circuit of the present invention:

The gate driving circuit provided in this embodiment includes a loading circuit, which is used for loading the first gate driving voltage on the gate of the pixel whose data driving voltage is a positive polarity signal, and loading the first gate driving voltage when the data driving voltage is a negative polarity signal. The gates of the pixels are loaded with a second gate driving voltage, wherein the first gate driving voltage is higher than the second gate driving voltage.

The gate drive circuit provided in this embodiment can be applied to the above four drive modes. By applying a second gate drive voltage with a lower voltage to the gate of a pixel whose data drive voltage is a negative polarity signal, the TFT The grid bias problem prolongs the service life of the TFT; compared with the prior art, the power consumed by loading the second grid driving voltage is small, which saves the power consumption of the liquid crystal panel.

Embodiment 2 of the gate drive circuit of the present invention:

FIG. 2 is a schematic structural diagram of Embodiment 2 of the gate driving circuit of the present invention. As shown in FIG. 2 , this embodiment includes: a loading circuit 1 and a shift register 2 , wherein the shift register 2 is connected to the loading circuit 1 .

The loading circuit 1 is used for loading the first gate driving voltage on the gate of the pixel whose data driving voltage is a positive polarity signal, and loading the second gate driving voltage on the gate of the pixel whose data driving voltage is a negative polarity signal, The first gate driving voltage is higher than the second gate driving voltage, and the first gate driving voltage and the second gate driving voltage are obtained by the loading circuit 1 according to the third gate driving voltage output by the shift register 2 .

Specifically, the shift register 2 outputs the third gate driving voltage to the loading circuit 1, and the loading circuit 1 respectively obtains the first gate driving voltage and the second gate driving voltage according to the third gate driving voltage, and then respectively loads the on the gate of the corresponding pixel.

The above-mentioned shift register 2 can be a component that provides a gate driving voltage for a row of pixels of a frame of image signal in an existing liquid crystal display panel. In this embodiment, the newly added loading circuit 1 is connected between the shift register 2 and the gate of the pixel. In between, it is used to process the third gate driving voltage provided by the shift register 2 to obtain the first gate driving voltage and the second gate driving voltage, and then load them on the gate of the corresponding pixel.

Embodiment 3 of the gate drive circuit of the present invention:

FIG. 3 is a schematic structural diagram of Embodiment 3 of the gate driving circuit of the present invention. FIG. 3 only shows the driving circuit for the gate of the nth row of pixels. As shown in Figure 3, this embodiment specifically includes: a loading circuit 10 and a shift register 11, wherein the loading circuit 10 includes a first circuit 12 and a second circuit 13, wherein the first circuit 12 and the second circuit 13 are respectively connected to the shift register Register 11 is connected.

The shift register 11 specifically includes TFT switching devices T1, T2, T3 and T4, wherein the gate and source of T1 are connected to the output signal of the n-1 row pixel gate drive circuit shift register; the source of T2 is connected to the The drain is connected, the gate of T2 is connected to the output signal of the shift register of the n+1 row pixel gate drive circuit, the drain of T2 is connected to the low-voltage signal Vss; the gate of T3 is connected to the drain of T1, and the source of T3 is connected The clock signal CLK1, the drain of T3 is used to output the output signal of the shift register 11 of the pixel gate drive circuit of the nth row; the source of T4 is connected to the drain of T3, and the gate of T4 is connected to the pixel gate of the n+1th row The output signal of the shift register of the driving circuit, and the drain of T4 is connected to the low-voltage signal Vss.

The basic working principle of the above-mentioned shift register 11 is: when the output signal of the shift register of the n-1 row pixel gate drive circuit is a high-voltage signal, the shift register 11 is triggered to output CLK1, and when the n+1 row pixel gate When the output signal of the shift register of the driving circuit is a high-voltage signal, the shift register 11 is triggered to output a low-voltage signal. Specifically, when the gate of T1 receives a high-voltage signal, T1 is turned on, T1 outputs the high-voltage signal to the gate of T3, T3 is turned on, and T3 outputs CLK1. When CLK1 is the turn-on voltage of the nth row of pixels, T3 will The turn-on voltage is output as the gate drive voltage of the pixels in the nth row; when the gates of T2 and T4 receive a high-voltage signal, T2 and T4 are turned on, T2 outputs Vss to the gate of T3, T3 is turned off, and T4 outputs Vss, Make the shift register 11 output a low-voltage signal, that is, stop outputting the gate driving voltage of the pixels in the nth row.

As shown in FIG. 3 , one end of the first circuit 12 is connected to the first clock signal CLK2, and the first circuit 12 is used to apply the first gate driving voltage to the gate of the pixel whose data driving voltage is a positive polarity signal when CLK2 is at an on-level. , the first gate driving voltage is obtained by the first circuit 12 according to the third gate driving voltage output by the shift register 11 . As a preferred implementation manner, the first circuit 12 may include a first TFT switch device A1, A1 has a relatively large width-to-length ratio (Width/Length, W/L for short), and it can nearly complete the input signal output, that is, when the input signal of A1 is the third gate driving voltage, the first gate driving voltage output by A1 is close to or equal to the third gate driving voltage. Specifically, the gate of A1 is connected to the first clock signal CLK2, the drain of A1 is connected to the shift register 11, specifically the drain of T3, and the source of A1 outputs the first gate driving voltage. When the first clock signal CLK2 is the turn-on voltage of the nth row of pixels whose data drive voltage is a positive polarity signal, A1 is turned on, and A1 completes the first gate drive voltage which is close to or equal to the third gate drive voltage output by T3 The output to the gate of the nth row of pixels.

As shown in FIG. 3 , one end of the second circuit 13 is connected to the second clock signal CLK3, and the second circuit 13 is used to apply the second gate driving voltage to the gate of the pixel whose data driving voltage is a negative polarity signal when CLK3 is at an on level. , the second gate driving voltage is obtained by the second circuit 13 according to the third gate driving voltage output by the shift register 11 . As a preferred implementation manner, the second circuit 13 may include a second TFT switching device A2, the W/L of A2 is relatively small, and the W/L of A2 is smaller than that of A1, which can reduce the higher input signal voltage to output, that is to say, when the input signal of A2 is the third gate drive voltage, the second gate drive voltage output by A2 is smaller than the third gate drive voltage, so the second gate drive voltage is also smaller than the first gate drive voltage pole drive voltage. Specifically, the gate of A2 is connected to the second clock signal CLK3, the drain of A2 is connected to the shift register 11, specifically the drain of T3, and the source of A2 outputs the first gate driving voltage. When the second clock signal CLK3 is the turn-on voltage of the nth row of pixels whose data driving voltage is a negative polarity signal, A2 reduces the third gate driving voltage output by T3 to obtain the second gate driving voltage and outputs it to the nth row pixel grid.

In the gate drive circuit provided by the present invention, the first circuit and the second circuit are not limited to TFT switching devices, other devices that can realize the above functions all belong to the scope of protection of the present invention, for example, the first circuit and the second circuit can be resistors In the circuit formed, the resistance value of the first circuit can be set very small, so that the first gate driving voltage is slightly lower than the third gate driving voltage, and the resistance value of the second circuit is set larger, so that the second gate driving voltage is much smaller than third gate drive voltage.

Further, this embodiment may also include a seventh TFT switching device T7, the gate of T7 is connected to the output terminal of the shift register of the pixel gate driving circuit in the n+1th row (ie, the next row), and the drain of T7 is connected to the low-voltage signal Vss and the source of T7 are connected to the sources of A1 and A2 respectively. When the gate of T7 receives a high-voltage signal, T7 is turned on, and T7 outputs Vss, so that A1 and A2 output a low-voltage signal, that is, stop outputting the gate driving voltage of the nth row of pixels.

The gate driving circuit provided in this embodiment can be used in the frame inversion driving mode and the row inversion driving mode. The gate line of each row of pixels of the liquid crystal display panel is connected with a gate driving circuit as shown in FIG. 3 , and the gate driving circuit shown in FIG. 3 Both output lines of the shown gate drive circuit are connected to the same gate line. The above-mentioned first clock signal CLK2 and second clock signal CLK3 are turned on alternately with at least one frame unit inversion. When used in the frame inversion driving mode and the row inversion driving mode, the first clock signal CLK2 and the The second clock signal CLK3 alternately provides the turn-on level with the inversion of the frame.

Embodiment 4 of the gate drive circuit of the present invention:

FIG. 4 is a schematic structural diagram of Embodiment 4 of the gate driving circuit of the present invention. FIG. 4 only shows the driving circuit for the gate of the nth row of pixels. As shown in Figure 4, this embodiment specifically includes: a loading circuit 20 and a shift register 11, wherein the loading circuit 20 includes a third circuit 21, a fourth circuit 22, a fifth circuit 23 and a sixth circuit 24, wherein the third circuit 21. The fourth circuit 22, the fifth circuit 23 and the sixth circuit 24 are respectively connected to the shift register 11.

The structure and working principle of the shift register 11 are the same as those in the third embodiment, and will not be repeated here.

As shown in FIG. 4, one end of the third circuit 21 and one end of the fourth circuit 22 are both connected to the third clock signal CLK4, and the third circuit 21 is used for gates of pixels whose data drive voltage is a positive polarity signal when CLK4 is at an on level. Loading the first gate driving voltage, the first gate driving voltage is obtained by the third circuit 21 according to the third gate driving voltage output by the shift register 11; the fourth circuit 22 is used when CLK4 is at the turn-on level, The second gate driving voltage is applied to the gate of the pixel whose data driving voltage is a negative polarity signal, and the second gate driving voltage is obtained by the fourth circuit 22 according to the third gate driving voltage output by the shift register 11 . As a preferred implementation manner, the third circuit 21 includes a third TFT switch device A3, the fourth circuit 22 includes a fourth TFT switch device A4, and the W/L of A3 is greater than A4. The W/L of A3 is relatively large, it can output the input signal almost completely, the W/L of A4 is relatively small, it can reduce the high input signal voltage and output it, that is to say, when A3 and A4 When the input signal is the third gate driving voltage, the first gate driving voltage output by A3 is close to or equal to the third gate driving voltage, and the second gate driving voltage output by A4 is smaller than the third gate driving voltage, so that The second gate driving voltage is also smaller than the first gate driving voltage. Specifically, the gates of A3 and A4 are connected to the third clock signal CLK4, the drains of A3 and A4 are connected to the shift register 11, specifically connected to the drain of T3, the source of A3 outputs the first gate driving voltage, and the source of A4 The pole outputs the second gate driving voltage. When the third clock signal CLK4 is the turn-on voltage of the pixels in the nth row of the nth frame, A3 and A4 are turned on, and A3 completely outputs the first gate driving voltage which is close to or equal to the third gate driving voltage output by T3 to For the gates of some pixels in the nth row of the nth frame, the data driving voltage of this part of the pixels is a positive polarity signal. A4 reduces the third gate driving voltage output by T3 to obtain the second gate driving voltage and outputs it to the nth frame. The gates of another part of pixels in n rows, the data driving voltage of this other part of pixels is a negative polarity signal.

4, one end of the fifth circuit 23 and one end of the sixth circuit 24 are both connected to the fourth clock signal CLK5, and the fifth circuit 23 is used for gates of pixels whose data drive voltage is a negative polarity signal when CLK5 is at an on level. The second gate driving voltage is applied to the top, and the second gate driving voltage is obtained by the fifth circuit 23 according to the third gate driving voltage output by the shift register 11; the sixth circuit 24 is used when CLK5 is at an on level, The first gate driving voltage is applied to the gate of the pixel whose data driving voltage is a positive polarity signal, and the first gate driving voltage is obtained by the sixth circuit 24 according to the third gate driving voltage output by the shift register 11 . As a preferred implementation manner, the fifth circuit 23 includes a fifth TFT switch device A5, the sixth circuit 24 includes a sixth TFT switch device A6, and the W/L of A6 is greater than A5. The W/L of A5 is relatively small, it can reduce the high input signal voltage and output it, the W/L of A6 is relatively large, it can output the input signal almost completely, that is to say, when A5 and A6 When the input signal is the third gate driving voltage, the second gate driving voltage output by A5 is smaller than the third gate driving voltage, and the first gate driving voltage output by A6 is similar to or equal to the third gate driving voltage, so that The second gate driving voltage is also smaller than the first gate driving voltage. Specifically, the gates of A5 and A6 are connected to the fourth clock signal CLK5, the drains of A5 and A6 are connected to the shift register 11, specifically connected to the drain of T3, the source of A5 outputs the second gate driving voltage, and the source of A6 The pole outputs the first gate driving voltage. When the fourth clock signal CLK5 is the turn-on voltage of the pixels in the nth row of the n+1th frame, A5 and A6 are turned on, and A5 reduces the third gate driving voltage output by T3 to obtain the second gate driving voltage and output it to the nth For the gates of some pixels in the nth row of +1 frame, the data driving voltage of this part of pixels is a negative polarity signal, and A6 will completely output the first gate driving voltage which is similar to or equal to the third gate driving voltage output by T3 to For the gates of another part of the pixels in the nth row of the n+1th frame, the data driving voltage of the other part of the pixels is a positive polarity signal.

In the gate drive circuit provided by the present invention, the third circuit, the fourth circuit, the fifth circuit and the sixth circuit are not limited to TFT switching devices, other devices that can realize the above functions all belong to the protection scope of the present invention, for example, they can In a circuit composed of resistors, the resistance values of the third circuit and the sixth circuit can be set very small so that the first gate driving voltage is slightly smaller than the third gate driving voltage, and the resistance values of the fourth circuit and the fifth circuit are set to be larger , making the second gate driving voltage much smaller than the third gate driving voltage.

In this embodiment, the connection relationship and working mode of the TFT switching device T7 are the same as those in the third embodiment.

The gate drive circuit provided in this embodiment can be used in a 1-dot interlaced inversion driving mode and a 2-dot interlaced inversion driving mode. The gate lines of each row of pixels of the liquid crystal display panel are connected to a gate drive circuit as shown in FIG. 4 , And the two output lines of the gate driving circuit shown in FIG. 4 are connected to different gate lines of the same row of pixels. The above-mentioned third clock signal CLK4 and fourth clock signal CLK5 are turned on alternately with at least one frame unit inversion. The clock signal CLK4 and the fourth clock signal CLK5 alternately provide the turn-on level with the inversion of the frame.

For the above-mentioned 1-dot interlaced inversion driving method and 2-dot interlaced inversion driving method, the data driving voltage of some pixels in the same row of pixels is a positive polarity signal, and the data driving voltage of another part of pixels is a negative polarity signal. The invention also provides a pixel structure, including at least one row of pixels and two gate signal lines for driving one row of pixels, and the two gate signal lines are respectively used for applying the first gate driving voltage and the second gate driving voltage . The gate signal line loaded with the first gate driving voltage is used to drive the pixels whose data driving voltage is a positive signal in a row of pixels; the gate signal line loaded with the second gate driving voltage is used to drive the data driving voltage of a row of pixels Pixels with negative polarity signals. For different driving modes, the corresponding pixel structures are introduced in detail below.

Embodiment 1 of the pixel structure of the present invention:

FIG. 5 is a schematic structural diagram of Embodiment 1 of the pixel structure of the present invention. This pixel structure corresponds to the 1-dot interlaced inversion driving method. Only two rows of pixels are shown in FIG. These are gate signal lines 41 and gate signal lines 42. The gate signal lines 41 are used to drive the pixels 43 whose data drive voltage in a row of pixels is a positive polarity signal, and the gate signal lines 42 are used to drive the data drive voltage in a row of pixels. The voltage is the pixel 44 of the negative polarity signal.

For the first row of pixels in FIG. 5, the data drive voltage of the pixel 43 at the current moment is a positive polarity signal (indicated by "+" in the figure), and the gate signal line 41 is loaded with the first gate drive voltage; The data driving voltage is a negative polarity signal (indicated by “-” in the figure), and the gate signal line 42 is loaded with the second gate driving voltage, wherein the first gate driving voltage is higher than the second gate driving voltage.

The pixel structure of this embodiment can adopt the gate driving circuit provided in FIG. 4 , specifically, the two output lines in FIG. 4 are respectively connected to the gate signal lines 41 and 42 in FIG. 5 .

In this embodiment, two gate signal lines are used to drive a row of pixels, and different gate driving voltages can be applied to the gates of pixels with positive and negative signals, and specifically, the gates of pixels with negative signals can be loaded with The second gate drive voltage with lower voltage effectively alleviates the problem of TFT gate bias and prolongs the service life of TFT; compared with the prior art, the power consumed by loading the second gate drive voltage is less , saving the power consumption of the LCD panel.

FIG. 6 is a schematic structural diagram of Embodiment 2 of the pixel structure of the present invention. This pixel structure corresponds to the 2-dot interlaced inversion driving method. Only two rows of pixels are shown in Figure 6. For each row of pixels, it is assumed that it includes multiple groups, each group includes 2 adjacent pixels, and two grids The polar signal lines are gate signal lines 51 and gate signal lines 52 respectively, the gate signal lines 51 are used to drive the pixels 53 whose data driving voltage is a positive polarity signal in a row of pixels, and the gate signal lines 52 are used to drive a row of pixels The data drive voltage in the pixel 54 is a negative polarity signal.

For the first row of pixels in FIG. 6 , the data drive voltage of the pixel 53 at the current moment is a positive polarity signal (indicated by "+" in the figure), and the gate signal line 51 is loaded with the first gate drive voltage; The data driving voltage is a negative polarity signal (indicated by “-” in the figure), and the gate signal line 52 is loaded with the second gate driving voltage, wherein the first gate driving voltage is higher than the second gate driving voltage.

In this embodiment, one of the two gate signal lines is used to drive odd groups of pixels in a row of pixels, and the other gate signal line is used to drive even groups of pixels in a row of pixels.

The pixel structure of this embodiment may adopt the gate driving circuit provided in FIG. 4 , specifically, the two output lines in FIG. 4 are respectively connected to the gate signal lines 51 and 52 in FIG. 6 .

In this embodiment, two gate signal lines are used to drive a row of pixels, and different gate driving voltages can be applied to the gates of pixels with positive and negative signals, and specifically, the gates of pixels with negative signals can be loaded with The second gate drive voltage with lower voltage effectively alleviates the problem of TFT gate bias and prolongs the service life of TFT; compared with the prior art, the power consumed by loading the second gate drive voltage is less , saving the power consumption of the LCD panel.

The present invention can also provide a pixel structure for multi-dot (greater than 2 dots) interlaced inversion driving mode, wherein each row of pixels is divided into multiple groups, and the difference from the above-mentioned embodiment is that each group includes more than 3 adjacent pixels.

Those of ordinary skill in the art can understand that all or part of the steps for realizing the above-mentioned method embodiments can be completed by hardware related to program instructions, and the aforementioned program can be stored in a computer-readable storage medium. When the program is executed, the The steps of the above-mentioned method embodiments are included, and the aforementioned storage medium includes: ROM, RAM, magnetic disk or optical disk, and other various media that can store program codes.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: it can still be Modifications are made to the technical solutions described in the foregoing embodiments, or equivalent replacements are made to some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims (10)

1. A gate driving method, characterized in that, comprising: The first gate driving voltage is applied to the gate of the pixel whose data driving voltage is a positive polarity signal, and the second gate driving voltage is applied to the gate of a pixel whose data driving voltage is a negative polarity signal, and the first gate The driving voltage is higher than the second gate driving voltage. 2. A gate drive circuit, characterized in that it includes: a loading circuit for loading a first gate drive voltage on the gate of a pixel whose data drive voltage is a positive polarity signal, and when the data drive voltage is a negative polarity signal Loading a second gate driving voltage on the gate of the pixel of the signal; The first gate driving voltage is higher than the second gate driving voltage. 3. The gate drive circuit according to claim 2, further comprising: a shift register connected to the loading circuit; The first gate driving voltage and the second gate driving voltage are obtained by the loading circuit according to the third gate driving voltage output by the shift register. 4. The gate drive circuit according to claim 2 or 3, wherein the loading circuit comprises: The first circuit is used to apply the first gate driving voltage to the gate of the pixel whose data driving voltage is a positive polarity signal when the first clock signal is at the turn-on level; The second circuit is used to apply a second gate driving voltage to the gate of the pixel whose data driving voltage is a negative polarity signal when the second clock signal is at an on level; The first clock signal and the second clock signal are alternately turned on as they are inverted in units of at least one frame. 5. The gate drive circuit according to claim 4, wherein the first circuit comprises a first TFT switch device, the second circuit comprises a second TFT switch device, and the first TFT switch device a width-to-length ratio greater than that of the second TFT switch device; The gate of the first TFT switch device is connected to the first clock signal, the drain of the first TFT switch device is connected to a shift register, and the source of the first TFT switch device outputs the first gate driving voltage; The gate of the second TFT switch device is connected to the second clock signal, the drain of the second TFT switch device is connected to the shift register, and the source of the second TFT switch device outputs the second gate driving voltage. 6. The gate drive circuit according to claim 5, wherein the loading circuit further comprises a seventh TFT switching device; The gate of the seventh TFT switch device is connected to the output end of the shift register of the next row of pixels, the drain of the seventh TFT switch device is connected to a low-voltage signal, and the source of the seventh TFT switch device is connected to the first A source of a TFT switch device and a source of the second TFT switch device. 7. The gate drive circuit according to claim 2 or 3, wherein the loading circuit comprises: The third circuit is used to apply the first gate driving voltage to the gate of the pixel whose data driving voltage is a positive polarity signal when the third clock signal is at the turn-on level; The fourth circuit is used to apply the second gate driving voltage to the gate of the pixel whose data driving voltage is a negative polarity signal when the third clock signal is at the turn-on level; The fifth circuit is used to apply the second gate driving voltage to the gate of the pixel whose data driving voltage is a negative polarity signal when the fourth clock signal is at the turn-on level; The sixth circuit is used to apply the first gate driving voltage to the gate of the pixel whose data driving voltage is a positive polarity signal when the fourth clock signal is at the turn-on level; The third clock signal and the fourth clock signal are alternately turned on as they are inverted in units of at least one frame. 8. The gate drive circuit according to claim 7, wherein the third circuit includes a third TFT switching device, the fourth circuit includes a fourth TFT switching device, and the fifth circuit includes a fifth A TFT switch device, the sixth circuit includes a sixth TFT switch device, the width-to-length ratio of the third TFT switch device is greater than that of the fourth TFT switch device, and the width-to-length ratio of the sixth TFT switch device is greater than the a fifth TFT switch device; The gate of the third TFT switch device is connected to the third clock signal, the drain of the third TFT switch device is connected to the shift register, and the source of the third TFT switch device outputs the first gate driving voltage; The gate of the fourth TFT switch device is connected to the third clock signal, the drain of the fourth TFT switch device is connected to the shift register, and the source of the fourth TFT switch device outputs the second gate signal driving voltage; The gate of the fifth TFT switch device is connected to the fourth clock signal, the drain of the fifth TFT switch device is connected to the shift register, and the source of the fifth TFT switch device outputs the second gate signal driving voltage; The gate of the sixth TFT switch device is connected to the fourth clock signal, the drain of the sixth TFT switch device is connected to the shift register, and the source of the sixth TFT switch device outputs the first gate driving voltage. 9. A pixel structure comprising at least one row of pixels, further comprising: two gate signal lines for driving the row of pixels; the two gate signal lines are respectively used to load the first gate a drive voltage and a second gate drive voltage, the first gate drive voltage being higher than the second gate drive voltage; The gate signal line loaded with the first gate drive voltage is used to drive the pixels whose data drive voltage is a positive signal in the row of pixels; the gate signal line loaded with the second gate drive voltage is used to drive the row of pixels The middle data driving voltage is a pixel with a negative polarity signal. 10. The pixel structure according to claim 9, characterized in that: the row of pixels includes multiple groups, and a group of pixels includes at least one pixel; one gate signal line is used to drive the odd groups of pixels in the row pixels, and the other gate signal line is used to drive the even group of pixels in the row of pixels.

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