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area-CodeGen-coreclrCLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMICLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI
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Given sharplab
using System.Buffers;
using System.Runtime.CompilerServices;
public class C
{
public void M()
{
var amb = AsyncValueTaskMethodBuilder<ReadResult>.Create();
}
}
public readonly struct ReadResult
{
internal readonly ReadOnlySequence<byte> _resultBuffer;
internal readonly int _resultFlags;
}
The Jit zeros in the preamble with rep stosd
and then zeros in the body with vmovdqu
L0000: push rdi
L0001: push rsi
L0002: sub rsp, 0x38
L0006: vzeroupper
L0009: mov rsi, rcx
L000c: lea rdi, [rsp+0x8] ;
L0011: mov ecx, 0xc ;
L0016: xor eax, eax ;
L0018: rep stosd ; clear stack
L001a: mov rcx, rsi
L001d: lea rax, [rsp+0x8] ;
L0022: vxorps xmm0, xmm0, xmm0 ;
L0026: vmovdqu [rax], xmm0 ;
L002a: vmovdqu [rax+0x10], xmm0 ;
L002f: vmovdqu [rax+0x20], xmm0 ; clear stack again
L0034: add rsp, 0x38
L0038: pop rsi
L0039: pop rdi
L003a: ret
Would it be possible for the Jit to skip the second set of zeroing given its already zeroed the stack at the start?
category:cq
theme:prolog-epilog
skill-level:expert
cost:medium
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area-CodeGen-coreclrCLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMICLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI